Computer graphics processing and selective visual display system – Display peripheral interface input device – Light pen for fluid matrix display panel
Reexamination Certificate
1998-09-18
2001-09-25
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display peripheral interface input device
Light pen for fluid matrix display panel
C345S182000
Reexamination Certificate
active
06295048
ABSTRACT:
BACKGROUND
The invention relates to a system for positioning an output of a video display.
Continual advances in computer technology are making possible cost-effective, yet high performance computers capable of displaying high resolution images. A variety of display devices, including cathode ray tube (CRT) displays or thin-film-transistor (TFT) flat panel displays, may be used. These displays are driven by graphics peripherals such as video cards, which in turn are controlled by processors inside the computers.
Traditionally, due to their high cost, flat panel displays have been used only in notebook computers where size and low power requirements are important. As a notebook computer can drive its built-in flat panel display as well as an external CRT display, the video circuit of the notebook computer automatically handles differences between the CRT display and the flat panel display. In the controlled environment of the notebook computer, the maximum resolution of a flat panel display controller may be greater than or equal to that of the notebook computer's built-in flat panel display. However, in a desktop computer where a particular display attached to the desktop computer may be changed by a user, potential incompatibilities exist when a high resolution flat panel display is used with a desktop computer which is capable of driving only a low resolution flat panel display. For example, certain flat panel capable desktop computers are currently equipped with 65 megahertz (MHZ) video outputs and are limited to a resolution of 1024×768 pixels. When higher resolution flat panel displays become available, these flat panel displays may be incompatible with the original display circuits.
Computer systems capable of supporting both CRT displays as well as flat panel displays need to handle differences between the two types of display. For example, in the CRT display, an electron beam is swept horizontally across a line of the screen and, at the end of the line, the electron beam is moved vertically down to the next line before the horizontal sweep motion is repeated. Upon reaching the end of the screen, the electron beam is moved back to the origin of the screen and the process is repeated. These timing requirements are referred to as horizontal and vertical retrace timing requirements. The flat panel displays do not require as much time for horizontal and vertical blanking since they are digital devices which are addressed via internal counters and latches instead of an electron beam sweeping motion.
Also, each CRT display inherently has a variable resolution and accepts multiple input resolutions. “Multi-sync” circuitry is used to respond to video signals to control the CRT raster scan frequency. The CRT display's control signals include vertical sync (VSYNC), horizontal sync (HSYNC), and RED, GREEN, BLUE (RGB) signals. The HSYNC and VSYNC are signals defining horizontal and vertical raster frequency which are synchronized with the CRT display's logic. RED, GREEN and BLUE are analog signals which contain color data for each pixel. In contrast, the flat panel display operates at a fixed resolution and is controlled by video signals HSYNC, VSYNC, PIXCLOCK, RGBPIXDATA, and DATA_ENABLE. HSYNC and VSYNC are digital signals which provide similar function as the same named signals on a CRT interface. RGBPIXDATA is the digital RGB data and is typically 18-24 bits for each pixel. DATA_ENABLE identifies valid pixel data, which are latched with a pixel clock signal, PIXCLOCK.
Also, a flat panel display controller typically has a maximum resolution limited by a maximum clock frequency supported from its video output circuitry. The controller supports resolutions below the fixed resolution of its flat panel display via circuitry in the flat panel display controller. This circuitry provides at a minimum the ability to center a low resolution display on the panel. Other flat panel display controllers provide circuitry for upscaling the low resolution to the high native resolution of the panel using either pixel replication, or line replication, or interpolation with filtering at various quality levels. However, incompatibilities may exist between the display controller in the computer and the controller in the flat panel display and which may affect the display quality.
SUMMARY
An apparatus and a method allow an image to be positioned on a display device. The image to be centrally positioned may have one or more lines. The apparatus determines the number of black lines required to vertically center the image in a frame of the display device, where the top and bottom number of black lines is expressed as m and n, respectively. The apparatus displays m black lines using a first horizontal sync period at the start of each frame with the first horizontal sync period being less than the horizontal sync period of the display device. Each line of the image is then displayed, and subsequently n black lines are displayed using the second horizontal sync period until the end of the frame.
Implementations of the invention include one or more of the following. In the event the image is to be vertically centered, m equals n. Further, to horizontally center the image, the apparatus may determine the number of black pixels required to horizontally center the image in a frame of the display device on the left side as o and on the right side as p. The apparatus may then display o black pixels; displaying each line of the image next to the o black pixels; and displaying p black pixels within the first horizontal sync period. Additionally, for centering, o is constrained to equal p. The apparatus may also assert a vertical sync signal before generating the n horizontal sync signals. A third horizontal sync signal may be asserted after generating the m horizontal sync signals. The horizontal sync signal may be asserted for a specified duration. The apparatus may also include asserting a predetermined delay between the horizontal sync signal and a valid pixel signal. The the valid pixel signal may be a DATA_ENABLE signal. Further, the displaying of m black lines may include filling each pixel of a line buffer with a black value; and reading from the line buffer and rendering each of the m black lines using the first horizontal sync period or the second horizontal sync period.
Advantages of the invention may include one or more of the following. The video scaling circuit in the flat panel display device avoids a potential resolution incompatibility between the controller in the computer system and the controller in the peripheral flat panel display device. The system also automatically engages the scaler circuitry with the correct scaling factor based on an automatic mode detection process to migrate from a native flat panel display resolution. Further, the system provides software with a user interface for selecting the highest quality of all potential scaler modes when video scalers in the controller and in the display device have overlapping capabilities.
The scaler system is cost-effective since it flexibly handles the cost and quality tradeoffs required on both the system-side and the monitor-side. Cost sensitive systems or displays can implement minimal centering/scaling functions. High end systems can provide high quality scalers and achieve high quality images even when combined with low cost displays. Thus, the system allows the computer to control its ultimate video quality.
Additionally, the invention provides an automatic scaler mode selection process which avoids user intervention and which supports optimum image quality without requiring any expertise in manually configuring the computer and the display device.
The invention also provides a display with an optimized mode centering capability. The invention also minimizes the bandwidth needed between the system and display for centering a lower resolution display mode on a higher resolution display by varying the line frequency so that it is much higher during times where no pixel data is supplied.
Other features and advantage
D'Souza Henry M.
Reinke Mark L.
Ward Paul A.
Akin Gump Strauss Hauer & Feld & LLP
Compaq Computer Corporation
Hjerpe Richard
Laneau Ronald
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