Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-08-17
2001-08-14
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S063000, C257S616000, C257S607000, C438S285000
Reexamination Certificate
active
06274894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to short-channel transistor source and drain regions which are less susceptible to diffusion and allow improved control over transistor characteristics, and a method for fabricating these source and drain regions.
2. Description of the Relevant Art
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide (“oxide”), is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. The channel of the transistor is located under the gate dielectric, between the source and drain. A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors and interconnects, which have less than 0.3 &mgr;m critical dimension. As feature size decreases, the sizes of the resulting transistor and the interconnect between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
Such feature size reduction can place severe demands on reliable operation of the resulting transistors. For example, reduction in the transistor gate length can result in very high electric fields at the drain end of the transistor channel, unless the drain-to-source voltage used in operating the transistor is reduced by a corresponding amount. High electric fields can give rise to undesirable “hot carrier” effects in transistors, including avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric. These hot-carrier effects are typically mitigated by the use of dielectric sidewall spacers adjacent to sidewalls of the gate conductor. A relatively shallow impurity distribution, known as a lightly-doped drain (LDD) distribution, is first ion-implanted into the substrate using the gate conductor as a mask. The dielectric sidewall spacers are then formed, such that LDD portions adjacent the channel region are covered by the sidewall spacers. A deeper and somewhat more heavily doped impurity distribution is then implanted into the substrate using the gate conductor and sidewall spacers as a mask.
A cross-sectional view of an idealized MOSFET structure using LDD regions in the source and drain is shown in FIG.
1
. Gate conductor
14
is formed over gate dielectric
12
on semiconductor substrate
10
. LDD portions
18
are formed within substrate
10
before formation of dielectric sidewall spacers
16
. Deep source/drain portions
20
are formed by implantation into substrate
10
, aligned to sidewalls of spacers
16
. Portions
18
and
20
are of opposite impurity type than substrate
10
. For an n-channel transistor, for example, portions
18
and
20
are n-type, while substrate
10
is p-type. The doping of LDD portions
18
is somewhat lower than that of portions
20
, resulting in a lowered electric field associated with the p-n junction at the drain end of the MOSFET channel, thereby reducing the severity of hot-carrier effects. Furthermore, the small junction depth of LDD portions
18
reduces encroachment into the channel of the depletion region associated with the drain/channel p-n junction. This reduced depletion region encroachment may minimize other undesirable effects associated with short-channel transistors, as discussed in more detail below. The heavier doping and deeper extent of source/drain portions
20
aids in making contact to the source/drain regions.
A more realistic representation of a MOSFET with LDD regions is shown in FIG.
2
. The transistor of
FIG. 2
differs from that of
FIG. 1
in that LDD portions
18
are partially below gate conductor
14
, rather than being aligned under spacers
16
. In addition, source/drain portions
20
are partially below spacers
16
, rather than being aligned outside of spacers
16
. This change in the position of portions
18
and
20
from the as-implanted distributions is a result of diffusion of the implanted impurities during the subsequent fabrication steps. The speed and extent of this diffusion is enhanced by the presence of structural defects introduced into substrate
10
during ion implantation of portions
18
and
20
. Such defect-enhanced diffusion is also referred to as “transient-enhanced diffusion” (TED), wherein defects or other incidences of nonuniform structure (such as doping nonuniformities) are termed “transients”. The movement of source/drain portions
18
and
20
undesirably decreases the effective length of the channel to a value smaller than that defined by the length of gate conductor
14
. Furthermore, the defect-enhanced diffusion of portions
18
and
20
may not occur in a reliable, repeatable way, making predictable device fabrication difficult.
An additional problem associated with the overlap of gate conductor
14
and LDD portions
18
in
FIG. 2
is an increased overlap capacitance between the gate and the source or drain. This overlap capacitance, along with other capacitances and resistances associated with the transistor structure, contributes to an RC time constant which characterizes delays associated with signal propagation through a transistor circuit. Fabrication of a circuit with increased RC time constants lowers the speed at which the circuit can operate by increasing the time needed, for example, for a circuit output voltage to respond to a change in input voltage. The undesirable diffusion of LDD portions
18
into the channel of the transistor of
FIG. 2
can be reduced somewhat by keeping the doping of LDD portions
18
relatively low. However, this places an undesirable constraint on the doping of the LDD regions. The term “lightly-doped drain” implies a low doping in the LDD regions, and this has been the case historically. In current high-performance MOSFETs, however, the “LDD” region doping level is often within an order of magnitude of the doping level of the deep, heavily-doped source/drain portions. This increased LDD doping level reduces the series resistance of the LDD region, thereby increasing the transistor drive current. Lowering the doping level of the LDD region to mitigate the defect-enhanced diffusion of ion-implanted LDD regions may therefore increase the LDD series resistance and lower the transistor drive current.
In addition to the hot-carrier effects described above, other undesirable effects are associated with reduced feature sizes, and particularly shortened channel lengths, in MOSFETs. Some of these short-channel effects are associated with encroachment into the channel area of depletion regions from the drain/channel and source/channel p-n junctions. High electric fields within the drain/channel depletion region are associated with the hot-carrier effects described above. Under some conditions in a short-channel device, the depletion regions associated with the source/channel and drain/channel junctions may actually become joined in an area below the transistor channel. This joining of depletion regions, known as “punchthrough”, creates a path for drift of carriers from the source to the drain other than the intended transistor channel, and can lead to a loss of control of the channel by the transistor gate. Another short-channel effect related to the drain/channel and source/channel depletion regions is threshold voltage reduction, described in more detail below.
Feature size reduction drives a reduction of overall transistor dimensions and operating voltages known as “scaling”. As gate conductor widths decrease, for example, other device dimensions must also decrease in orde
Hause Frederick N.
Horstmann Manfred
Wieczorek Karsten
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Saadat Mahshid
Wilson Allan R.
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