Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-09-20
2004-10-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S660000, C438S690000, C257S048000
Reexamination Certificate
active
06800495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits (ICs), and more particularly to the manufacture and reliability of integrated circuits.
2. Description of the Background Art
Semiconductor manufacturers who make integrated circuit chips begin by fabricating semiconductor wafers. Each wafer is typically 100 mm, 125 mm, 150 mm, 200 mm or 300 mm in diameter and contains anywhere from one to several thousand chips or dice on the wafer. In the future, wafer sizes for semiconductor manufacturing are expected to continue to increase. When manufacture of the wafer is completed, chips or dice are cut or “diced” from the wafer and may later be mounted into single chip or multiple chip packages for implementation in a printed circuit board or other applications.
Reliability testing is used to screen out chips having an undesirable short life span. Typically, a significant percentage of a group of chips will fail early in their lifetime due to marginal conditions during manufacture. Subsequently, a very low percentage of the group will fail during an extended period of use of the chips. Reliability screening of semiconductor chips is typically performed by a process of supplying test signal patterns to chips under test to repeatedly stimulate substantially all devices and wires on a chip, and is typically performed at elevated temperatures to simulate or expedite the effects of the first months of operation. Therefore, the screening procedure is known as burn-in.
While very valuable, the process of burn-in has historically been time consuming and expensive for semiconductor manufacturers. Burn-in testing is typically conducted at temperatures in excess of 100 degrees Celsius and for prolonged periods of time (for example, 40 to 80 hours) with the chip running at relatively high operating voltages. Obviously, this slow rate of reliability testing impedes volume production of functional semiconductors and adds tremendous cost.
Many manufacturers have attempted to address low throughput of known burn-in processes by creating burn-in boards onto which many diced chips are placed in chip packages, and then the packages go into sockets on the burn-in boards. Thereafter, each chip on the test board is simultaneously exercised with test patterns at elevated temperatures. Thus, many chips are burned-in at once. These systems effectively reduce the time required to burn-in a large volume of chips. However, the added cost of packaging defective or unreliable die is a significant shortcoming of such known burn-in processes.
Another technique performs burn-in on the diced chips prior to packaging. Bare die burn-in (BDBI) is used to provide Known Good Die (KGD) determinations for multichip module's (MCM's) and other bare die applications, such as, chip-on-board (COB). Without bare die burn-in, yield of MCM's (and other bare die applications) is severely impaired, resulting in higher product costs. A bare die is typically placed into a temporary package, and the burn-in test is performed. The required alignment and handling steps in this procedure add cost, process complexity, and time to provide bare dies that will be reliable or “Known Good.”
Another technique is to perform burn-in on whole or parts of whole wafers containing undiced integrated circuits or chips. This process is known as wafer level burn-in (WLBI). In wafer level burn-in, electrical terminals from a test apparatus are brought into intimate contact with contact pads of one or more chips. It is therefore less destructive and costly than soldering chips to a burn-in board.
While progress has been made in burn-in processes, further improvement is desired to improve throughput of these processes.
SUMMARY
The invention relates to wafer level burn-in of integrated circuits on a semiconductor wafer. One embodiment of the invention performs monitored burn-in on sample wafers from a manufactured lot of wafers and determines a burn-in time for the lot from results of the monitored burn-in. The burn-in on remaining wafers from the lot is then performed for the burn-in time that was determined.
Another embodiment of the invention performs burn-in on wafers from a manufactured lot of wafers while monitoring in real-time the burn-in for a subset of wafers in the lot. Using fallout data from the real-time monitoring, a determination is made as to whether the burn-in time is sufficient. If the burn-in time is determined to be sufficient, then the burn-in of the lot is stopped.
These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims.
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Jin Bo
Payan Cesar
Cypress Semiconductor Corporation
Luk Olivia T.
Niebling John F.
Okamoto & Benedicto LLP
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