Lossless co-planar wave guide in CMOS process

Details Lossless co-planar wave guide in CMOS process Lossless co-planar wave guide in CMOS process

2006-07-25

2006-07-25

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S274000, C333S033000, C333S034000, C385S014000

Reexamination Certificate

active

07081648

ABSTRACT:
A structure and method of manufacturing a CMOS device where the Coplanar wave guide (CPW) lines are formed above the top metal lines. Also other insulating layers are provided that reduce the e-field from the signal line to the substrate. There are four embodiments. In the first embodiment, the following layers are formed over the semiconductor structure: the passivation layer, a shielding layer, a first insulator layer, a high K dielectric layer, a CPW and a second insulator layer. In the second embodiment, no shielding layer is used and the high k dielectric layer is thicker than in the first embodiment. In the third embodiment, a thick shielding layer is used and no high k dielectric layer. In the fourth embodiment, the top metal layer is used as a shielding layer and no high k dielectric layer is used.

REFERENCES:
patent: 4587541 (1986-05-01), Dalman et al.
patent: 5256996 (1993-10-01), Marsland et al.
patent: 5571740 (1996-11-01), Peterson
patent: 6490379 (2002-12-01), Boudreau et al.

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