Loss-of-signal detector for clock/data recovery circuits

Details Loss-of-signal detector for clock/data recovery circuits Loss-of-signal detector for clock/data recovery circuits

2000-08-17

2002-04-23

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By presence or absence pulse detection

C327S024000, C327S156000

Reexamination Certificate

active

06377082

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communications, and, in particular, to circuitry for detecting a loss of signal during communications over, for example, optical fibers.
2. Description of the Related Art
FIG. 1
shows a block diagram of a conventional clock/data recovery (CDR) circuit
100
suitable for applications such as 9.953-Gb/s fiber optic communications. CDR circuit
100
employs a phase-locked loop (PLL) that extracts a 9.953-GHz clock from an NRZ (non-return-to-zero) input data signal and recovers the data using this recovered clock. In this particular example, the recovered data is then de-multiplexed into a 16-bit parallel stream with each of the 16 outputs having a data rate of 622 Mb/s.
In particular, comparator
108
(e.g., a differential amplifier) of decision circuit
106
receives input data signal
102
and a stable decision threshold signal
104
(typically set to the midpoint between logic “0” and logic “1” voltage levels) and generates a difference signal
110
based on the difference between the input data signal and the decision threshold signal. Difference signal
110
is then input to a conventional charge-pump PLL consisting of phase detector (PD)
120
, charge pump (CP)
122
, loop filter (LF)
124
, and voltage-controlled oscillator (VCO)
126
. The PLL generates the 9.953-GHz recovered clock signal
128
, which is used to trigger a flip-flop
112
in decision circuit
106
that samples difference signal
110
to generate a 9.953-Gb/s recovered data signal
114
, which is then de-multiplexed by 1:16 demux
116
into 16-bit parallel recovered data stream
118
. Frequency acquisition circuit
130
uses input data signal
102
to generate estimated frequency
132
, a rough estimate of the frequency of the input data signal that is used to tune VCO
126
to the appropriate frequency range.
One of the challenges in implementing a CDR circuit, such as CDR circuit
100
of
FIG. 1
, is the problem of detecting when the input data signal no longer contains valid data. For example, in optical fiber communications, it is desirable to be able to detect the loss of signal that results when the fiber to the photo-diode (which converts the received optical signal into electrical input data signal
102
and which is not shown in
FIG. 1
) is cut, which may result in one of the following input signal conditions:
Input data switching randomly;
Input data switching synchronously with the local VCO (due to unintentional feedback); or
Input data stuck at logic “1” (referred to as a “stuck-at-one” condition) or stuck at logic “0” (referred to as a “stuck-at-zero” condition). To address the possibility of these different conditions, conventional CDR circuits are implemented with a loss-of-signal (LOS) detector that is designed to detect different input signal conditions that can result from failures such as cut fibers. For example, conventional CDR circuit
100
of
FIG. 1
comprises LOS detector
134
, which processes input data signal
102
to generate LOS signal
136
, which is sent off chip to indicate when an LOS condition has been detected (e.g., a logic “0” indicating a valid signal condition and a logic “1” indicating a detected LOS condition).
FIG. 2
shows a block diagram of a conventional LOS detector
200
used in CDR circuits, such as for LOS detector
134
in CDR circuit
100
of FIG.
1
. LOS detector
200
comprises two different circuits designed to detect different types of LOS conditions that may result from a cut fiber: a transition detector
201
for detecting stuck-at-one and stuck-at-zero conditions and an amplitude detection circuit (consisting of peak detector
203
and comparator
205
) for detecting when the input data signal has too low a peak-to-peak amplitude.
Transition detector
201
detects a stuck-at-one or a stuck-at-zero condition that may result when a fiber is cut. Transition detector
201
is a logic circuit that samples the input data signal
102
using the recovered clock signal
128
and counts the number of 0-to-1 and 1-to-0 transitions that occur. Transition detector
201
generates a high (i.e., logic “1”) output signal
207
if no transitions have occurred in a specified time period. Alternatively, transition detector
201
may produce a high output signal if less than K transitions are detected over a specified time period. Transition detector
201
may be implemented using either digital or mixed analog-digital circuit techniques.
The amplitude detection circuit of LOS detector
200
detects LOS situations in which the peak-to-peak amplitude of the input data signal remains below a certain level, such as may occur if the fiber is cut and the input data signal
102
is switching randomly with low peak-to-peak amplitude. The amplitude detection circuit will also detect LOS situations where the input data signal is switching synchronously with the VCO due to local feedback, where the crosstalk-induced data signal peak-to-peak amplitude is likely to be relatively low.
In particular, peak detector
203
estimates the peak value of input data signal
102
. The resulting peak signal
209
is subtracted from a stable LOS threshold signal
211
by comparator
205
to generate an output signal
213
, which is high (indicating an LOS signal) if peak signal
209
falls below LOS threshold signal
211
. Under normal operating conditions in which the input data signal contains valid data, the NRZ input data signal will be present at sufficient peak-to-peak amplitude such that peak signal
209
generated by peak detector
203
will remain above LOS threshold signal
211
.
Peak detector
203
is designed to have a leakage path through resistor R
droop
that provides “droop” (i.e., signal level decay). If the input data signal disappears or if its peak-to-peak amplitude does not reach a sufficiently high level with sufficient frequency, then peak signal
209
generated by peak detector
203
will slowly drop as a result of the leakage through resistor R
droop
. When peak signal
209
falls below LOS threshold signal level
211
, output signal
213
generated by comparator
205
will go high indicating an LOS condition.
Output signals
207
and
213
generated by transition detector
201
and comparator
205
, respectively, are input to OR gate
213
, which applies a logical “OR” operation to generate a high LOS signal
136
, if either or both of output signals
207
and
213
are high, indicating that an LOS condition has been detected.
Although LOS detector
200
of
FIG. 2
does a good job detecting certain LOS conditions, it does not provide reliable detection of an LOS condition in which the input data signal has a relatively large peak-to-peak amplitude and is switching randomly (i.e., not synchronously with the VCO). Such a situation could occur when a fiber cut occurs upstream of an optical amplifier, which would then be located between the fiber cut and the CDR circuit, where the optical amplifier contributes to generation of a noise-induced, randomly switching, large-amplitude input data signal. In another situation, crosstalk effects (asynchronous to the VCO) could produce large-amplitude noise. In each of these cases, since the input data signal will contain frequent zero crossings, transition detector
201
of LOS detector
200
will not detect an LOS condition. By the same token, since, in each of these cases, the input data signal will frequently achieve peak-to-peak amplitudes greater than LOS threshold
211
, the amplitude detection circuit of LOS detector
200
will not detect an LOS condition.
SUMMARY OF THE INVENTION
The present invention is directed to loss-of-signal detectors that are designed to detect LOS conditions that are not reliably detected by conventional LOS detectors, such as LOS detector
200
of FIG.
2
. In particular, in addition to the LOS conditions detected by such conventional LOS detectors, the LOS detectors of the present invention are designed to detect LOS conditions in which the input data signal has a relatively large peak-to-peak amplitude

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