Loss of clock detector circuit

Details Loss of clock detector circuit Loss of clock detector circuit

1978-08-09

1980-10-28

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

328120, 328151, H03K 519

Patent

active

042309581

ABSTRACT:
This invention involves a detector circuit in MOS technology for sensing "loss of clock"; that is, whenever a clock input voltage pulse source is interrupted or stops (becomes "stuck") at any level, the output voltage of the detector circuit is at a high level, but is at a low level when the clock is working properly. Such a circuit is achieved by means of a first MOS electrical inverter (I.sub.1), connected for feeding its output to an MOS electrical differentiator (.DELTA.), connector for feeding its output to a thresholding MOS amplifier (A), connected for feeding its output to a unidirectional MOS current inhibitor (D), connected for feeding its output to a second MOS electrical inverter (I.sub.2), connected in parallel with a storage capacitor (C) in parallel with a leakage current source (J.sub.L), whereby the output of the second inverter is a binary indication of the presence vs. absence of clock pulse input to the first inverter.

REFERENCES:
patent: 3153762 (1964-10-01), Johnson
patent: 3204189 (1965-08-01), Trautwein
patent: 3458822 (1969-07-01), Hahn, Jr.
patent: 3903474 (1975-09-01), Wiley
patent: 4004162 (1977-01-01), Kato et al.
patent: 4004164 (1977-01-01), Cranford, Jr. et al.
patent: 4047059 (1977-09-01), Rosenthal
patent: 4048518 (1977-09-01), Koo
patent: 4110748 (1978-08-01), Marino
patent: 4117348 (1978-09-01), Newman
patent: 4142159 (1979-02-01), Ingram et al.
Mellaert, "Computer Control Back-Up", IBM Tech. Discl. Bull., vol. 13, No. 5, pp. 1301-1302, 10/1970.

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