Multiplex communications – Wide area network – Packet switching
Patent
1987-03-25
1990-07-17
Orsino, Joseph A.
Multiplex communications
Wide area network
Packet switching
H04J 302
Patent
active
049425730
ABSTRACT:
A loosely coupled parallel network simulator has been described which employs a time multiplex bus to which a plurality of processing sites are coupled with each processing site being assigned one or more particular time slots during the bus cycle. Each processing site contains a sequencing RAM or control store which determines that clock time during the bus cycle that the processing site is to be given access for either transmission or reception of data segments.
REFERENCES:
patent: 4156112 (1979-05-01), Moreland
patent: 4488290 (1984-12-01), Dunn et al.
patent: 4535448 (1985-08-01), Baxter et al.
patent: 4538261 (1985-08-01), Rume
patent: 4631534 (1986-12-01), Franklin et al.
Bramson Robert S.
Orsino Joseph A.
Scutch III Frank M.
Sowell John B.
Starr Mark T.
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