Multiplex communications – Network configuration determination
Reexamination Certificate
2002-07-01
2008-12-30
Sam, Phirin (Department: 2619)
Multiplex communications
Network configuration determination
C712S010000, C712S011000
Reexamination Certificate
active
07471643
ABSTRACT:
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other clusters, via a dedicated multiplexer control network. Components of applications configured onto the array are selectively implemented in either multiplexers or ALUs, as determined by the relative efficiency of implementing the component in one or the other type of processing element, and by the relative availability of the processing element types. Multiplexer control signals are generated from combinations of ALU status signals, and optionally routed to control multiplexers in different clusters.
REFERENCES:
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 5038386 (1991-08-01), Li
patent: 5442577 (1995-08-01), Cohen
patent: 5715186 (1998-02-01), Curtet
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5914953 (1999-06-01), Krause et al.
patent: 6011795 (2000-01-01), Varghese et al.
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6157967 (2000-12-01), Horst et al.
patent: 6469540 (2002-10-01), Nakaya
patent: 6609189 (2003-08-01), Kuszmaul et al.
patent: 6781408 (2004-08-01), Langhammer
patent: 6807172 (2004-10-01), Levenson et al.
patent: 6907011 (2005-06-01), Miller et al.
patent: 6965615 (2005-11-01), Kerr et al.
patent: 7272691 (2007-09-01), Stewart et al.
patent: 2002/0010902 (2002-01-01), Chen et al.
patent: 2002/0138716 (2002-09-01), Master
patent: 2003/0200418 (2003-10-01), DeHon et al.
patent: 2004/0001445 (2004-01-01), Stansfield
patent: 2004/0027995 (2004-02-01), Miller et al.
patent: WO00/69073 (2000-11-01), None
patent: WO 2004/075403 (2004-09-01), None
Bursky, D. “PFGA Combines Multiple Serial Interfaces and Logic” Electronic Design, Penton Publishing, Cleveland, Ohio vol. 28, No. 20, Oct. 2, 2000, pp. 74-76, 78.
Anthony Stansfield and Ian Page, “The Design of a New FPGA Architecture”, 1995, Proceedings of FPL 1995 Conference, pp. 1-14.
“Vertex-II 1.5V Field-Programmable Gate Arrays”, Virtex-II Platform FPGA Handbook, Xilinx Inc, v1.0, Dec. 6, 2000, p. 47.
Alan Marshall et al., “A Reconfigurable Arithmetic Array for Multimedia Application”, Proceedings of the 1999 ACM/SIGDA 7th International Symposium on FPGA.
Kai Hwang, Advanced Computer Architecture, McGraw Hill, 1993, pp. 338-339.
Orrick Herrington & Sutcliffe LLP
Panasonic Corporation
Sam Phirin
LandOfFree
Loosely-biased heterogeneous reconfigurable arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Loosely-biased heterogeneous reconfigurable arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Loosely-biased heterogeneous reconfigurable arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4022095