Loop filter level detection circuit and method

Details Loop filter level detection circuit and method Loop filter level detection circuit and method

1996-06-20

1997-06-24

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 8, 331 14, 331 17, 327157, 327158, 327159, H03L 700, H03L 7089

Patent

active

056420820

ABSTRACT:
A loop circuit such as a delay lock loop or a phase lock loop includes circuitry for detecting when the output signal of the low-pass filter in the loop has either risen to a voltage which is relatively close to the power voltage of the circuit or has fallen to a voltage which is relatively close to the ground voltage of the circuit. In either case the circuitry reverses the significance of the phase frequency detector output signals that control whether the output voltage of the low-pass filter rises or falls. Alternatively or in addition, the phase frequency detector may be reset. Coarser adjustments may be made to the loop circuit downstream from the low-pass filter in response to a recurrence of the low-pass filter output voltage reaching either of the detected voltages mentioned above.

REFERENCES:
patent: 4871930 (1989-10-01), Wong et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5347233 (1994-09-01), Ishibashi et al.
U. Ko et al., "A 30-ps Jitter, 3.6-.mu.s Locking, 3.3-Volt Digital PLL For CMOS Gate Arrays", IEEE 1993 Custom Integrated Circuits Conference, pp. 23.3.1-4.
A. Efendovich et al., "Multi-Frequency Zero-Jitter Delay-Locked Loop", IEEE 1993 Custom Integrated Circuits Conference, pp. 27.1.1-4.
A. Efendovich et al., "Multifrequency Zero-Jetter Delay-Locked Loop", IEEE Journal of Solid-State Circuits, vol. 29, No. 1, Jan. 1994, pp. 67-70.
A. Walzman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock", IEEE International Solid-State Circuits Conference 1994, pp. 298-299.

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