Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-09-13
2002-08-20
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
Reexamination Certificate
active
06437615
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to phase-locked loop (PLL) circuits and, more specifically, to a loop filter employable in PLL circuits and a related method of generating an output signal.
BACKGROUND OF THE INVENTION
In modern digital electronic computers, cooperating sequential logic circuits, where each performs several routine operations, are each controlled by derivatives of a master clock signal. These derivative clock signals are typically synchronized within the system to assist in optimizing computer functions, although they often do not arrive at their intended destinations in proper synchronism. Reasons for such skew in the derivative signals include, for example, variations in signal propagation delay for each destination. As a result, combining several complex synchronous logic circuits within a system presents a challenge with respect to synchronizing the clock signals transmitted to the respective circuits therein.
As high density, high speed application specific integrated circuits (ASICs) and high density programmable logic devices (PLDs) become available, on-chip clock distribution becomes more important to the integrity and performance of the designs implemented in these devices. Unfortunately, with the advent of ASICs and high-density PLDs, difficulties in managing clock delay and clock skew on these devices has become substantial. Many existing solutions for such problems, such as hardwired clock trees, are less effective for the applications found in today's programmable logic market. As integration levels of microelectronic circuits and system complexity continue to increase, the routing or distribution of a master system clock has become even more critical. This challenge is especially exacerbated in view of ever increasing clock rates in today's powerful microprocessors.
A common solution is the incorporation of a circuit having a phase-locked loop (PLL) architecture to assist in synchronizing and controlling the timing of clock signals in such devices. Because of the advantages, employing a voltage controlled oscillator (VCO) in a clock management circuit to create a PLL architecture has continued to gain popularity among device designers. Such oscillators adjust the various signals, such that the internal clock signals correspond to, or vary as a function of, a reference signal derived from a master clock signal. By doing so, the PLL architecture provides feedback that is used to nullify clock distribution problems, such as skew and jitter, within the circuit by comparing the master clock signal with that of a feedback signal. The difference between the two signals is used in a feedback control system to bring the signals into a fixed phase relation. Logical circuits implemented with AND and NOR gates compare the master clock signal or reference signal with the feedback signal to provide an output signal to control the VCO. More specifically, the master clock signal is compared with the feedback signal and the output signal is generated in response to the difference. In addition, a frequency divider may also be included in the feedback path when frequency multiplication is desired.
In conventional devices, those skilled in the art understand that this process is typically performed by a phase detector and charge pump. The phase detector and charge pump provide a current with a value proportional to the phase difference between the master clock signal and the feedback signal. The charge pump current is then fed into a loop filter for conversion to a voltage output signal used to control the VCO to generate the desired signals. To generate a voltage output signal, loop filters are typically created using a simple capacitor circuit, such as the conventional loop filter
120
illustrated in FIG.
1
. As illustrated, a charge pump
110
is coupled in series with the loop filter
120
, which includes a capacitor C
1
(as well as other components not illustrated), and is used to generate a voltage output signal V
out
to control a voltage-controlled oscillator (not illustrated). Those skilled in the art understand that the loop filter
120
may be constructed adding resistors or other devices placed in series with the capacitor C
1
or by simply placing the capacitor C
1
in a “feed forward zero” circuit configuration, as is known in the art.
Regardless of the configuration, the charge pump
110
delivers a charge pump current I
cp
to the capacitor C
1
, which is to be converted to the voltage output signal V
out
by the loop filter
120
. As the charge pump current I
cp
passes through the capacitor C
1
, the capacitor C
1
becomes charged by a charge voltage &Dgr;V. As a result, a charge/discharge rate R
c/d
of the capacitor C
1
may be defined by the following equation:
R
c
/
d
=
Δ
V
Δ
t
=
I
cp
C
1
where &Dgr;t is the time during which the capacitor C
1
is charged or discharged. Typically, PLL architectures require a slow voltage variation across the filter capacitor C
1
or a small charge voltage &Dgr;V. Using the equation above it can seen that a slow voltage variation during charging or discharging results in a lower charge/discharge rate R
c/d
.
Although the goal of a low charge/discharge rate R
c/d
appears simple in theory, reducing the principle to actual practice has proven problematic. Specifically, the equation demonstrates that a lower charge/discharge rate R
c/d
may be attained by either decreasing the charge pump current I
cp
(directly proportional to the rate R
c/d
) charging the capacitor C
1
, or by increasing the capacitance (inversely proportional to the rate R
c/d
) of the capacitor C
1
. However, sustaining a low constant charge pump current I
cp
in an effort to lower the charge/discharge rate R
c/d
is problematic due to leakages that occur across the charge pump
110
, making the smaller charge pump current I
cp
difficult to control. As a result, manufacturers are left with the choice of increasing the capacitance in the loop filter. Unfortunately, the size of the capacitor C
1
is generally limited by the available area on a semiconductor chip. Due to the high cost of chip surface area and the continuing desire to miniaturize components, semiconductor manufacturers are understandably eager to avoid increasing the size of the capacitors.
Accordingly, what is needed in the art is an improved loop filter and related method of generating an output signal that do not suffer from the deficiencies associated with the conventional designs.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides an improved loop filter configured to generate a control signal. In one embodiment, the loop filter includes a capacitor having a charge rate proportional to a current therethrough and configured to provide an output signal therefrom. The loop filter also includes a current bypass circuit, coupled to the capacitor, configured to reduce the current through the capacitor and thereby reduce the charge rate of the capacitor.
In another aspect of the present invention, a method of generating an output signal is provided. In one embodiment, the method may include providing current through a capacitor having a charge rate proportional to the current and creating an output signal therefrom. The method further includes coupling a current bypass circuit with the capacitor. The method still further includes reducing the current through the capacitor with the current bypass circuit, thereby reducing the charge rate of the capacitor.
In yet another aspect, the present invention provides a PLL circuit including a comparator circuit configured to compare a phase of a feedback signal to a phase of an input signal and generate a signal as a function of the comparison. In addition, the PLL circuit may include a charge pump configured to generate a current as a function of the signal from the comparator circuit, as well as a loop filter couplable to the charge pump. In such an embodiment, the loop
Hitt Gaines & Boisbrun P.C.
LSI Logic Corporation
Nu Ton My-Trang
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