Loop back testing structure for high-speed serial bit stream...

Details Loop back testing structure for high-speed serial bit stream... Loop back testing structure for high-speed serial bit stream...

2007-12-25

2007-12-25

Orgad, Edan (Department: 2616)

Multiplex communications

Diagnostic testing

Loopback

C370S532000

Reexamination Certificate

active

10390490

ABSTRACT:
A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a loop back circuitry. A bit stream demultiplexer includes an input ordering block, a plurality of demultiplexers, and an output ordering block. During testing, the transmit multiplexing integrated circuit and the receive demultiplexing integrated circuit are coupled into a circuit tester. Then, a plurality of input lines of the transmit multiplexing integrated circuit are coupled to a plurality of output data lines of the circuit tester. A loop back output of the transmit multiplexing integrated circuit is then coupled to a loop back input of the receive demultiplexing integrated circuit. A plurality of output lines of the receive demultiplexing integrated circuit are coupled to a plurality of input data lines of the circuit tester. Further, loop back control signals of the transmit multiplexing integrated circuit and the receive demultiplexing integrated circuit are coupled to control outputs of the circuit tester. The circuit tester is then operated to test the functionality of the integrated circuits.

REFERENCES:
patent: 4835770 (1989-05-01), Hayano
patent: 5384773 (1995-01-01), Olnowich et al.
patent: 6026076 (2000-02-01), Habegger et al.
patent: 6810046 (2004-10-01), Abbas et al.
patent: 2003/0007516 (2003-01-01), Abramov et al.

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