Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – With auxiliary means to condition stimulus/response signals
Reexamination Certificate
1997-10-29
2001-02-06
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
With auxiliary means to condition stimulus/response signals
C341S110000
Reexamination Certificate
active
06184692
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the testing of a system which includes receiving and transmitting circuitry located in close proximity to each other, as in a telephone, and, in particular, to the concurrent testing of the receive and transmit circuitry.
A problem present in the prior art may be best explained with reference to
FIG. 1
which shows a device under test (DUT)
10
. DUT
10
includes a receive section
12
, a transmit section
14
and a lock-out circuit
16
designed to prevent oscillations due to feedback between the transmit and receive sections. Circuitry
12
,
14
,
16
may be mounted on a printed circuit board for subsequent installation in a telephone.
Receive section
12
includes an input circuit
121
, amplifying and processing circuitry
122
and
123
, and a digital-to-analog (D/A) converter circuit
124
. The output
125
of the A/D converter
124
is intended to be supplied via output lines
127
and
128
to a speaker
20
. The speaker
20
converts the analog signals it receives into audio signals.
A microphone
30
converts incoming audio signals into analog signals which are supplied via lines
137
and
138
to the input
140
of transmit section
14
. The input
140
of transmit section
14
is applied to an input circuit
141
whose output is supplied to amplifying and processing circuitry
142
and
143
. The output of circuit
143
is applied to an analog to digital (A/D) converter circuit
144
having an output
145
and two output lines
147
,
148
.
Lock-out circuit
16
includes: (a) circuitry responsive to signals being processed and propagated along the receive section
12
to prevent and inhibit the processing and propagation of signals along the transmit section
14
; and (b) circuitry responsive to signals being processed and propagated along the transmit section
14
to prevent and inhibit the processing and propagation of signals along the receive section
12
. Lock-out circuit
16
may be a sophisticated computer algorithm generated and driven by appropriate sensors. Lock out circuit
16
prevents the testing of sections
12
and
14
at the same time. Comparator
43
may be a sophisticated computer algorithm generated by tester
40
.
The DUT may be exercised and tested by means of a tester
40
which includes: (a) a digital tone generator (DTG)
41
, for supplying digital test signals via lines
117
and
118
to the input of the receive section
12
; (b) analog-to-digital (A/D) circuitry
42
for sensing the analog signals produced at the output
125
of the receive section
12
and converting these analog signals to corresponding digital signals; and (c) comparator circuitry
43
for comparing the digital signals supplied to receive system
12
with those received from the output of section
12
to determine the operability of receive section
12
. Tester
40
also includes: (a) a digital tone generator (DTG)
41
a
(which may be part of DTG
41
) for generating signals to be applied to the transmit section; (b) a digital-to-analog (D/A) circuit
44
, responsive to DTG
41
a
, for supplying analog signals to the input
140
of transmit section
14
; and (c) comparator means
45
for sensing the digital signals produced at the output (
145
) of transmit section
14
and for comparing the digital signals received from the transmit section with the digital signals supplied (via D/A
44
) to the input of the transmit section. Comparator
45
, like comparator
43
, may be a sophisticated computer algorithm generated by the tester.
As noted above, due to the presence of lock out circuit
16
, each one of sections
12
and
14
has to be tested separately. Due to the integrated design of the receive, transmit and lock-out sections, the lock out circuitry
16
can not be easily disabled during testing of the receive and transmit circuitry in DUT
10
.
Thus, in accordance with the prior art, sections
12
and
14
have to be tested separately one at a time. This is necessary since whenever one section is processing signals, it inhibits the other section from processing signals. However, it should be evident that this causes the testing of the receive and transmit channels to be inefficient.
Also, in the prior art system of
FIG. 1
, there is no mechanism provided to test the receive channel with its speaker and the transmit channel with its microphone, all at the same time.
The present invention resolves the defects and disadvantages discussed above.
SUMMARY OF THE INVENTION
Applicant's invention is applicable to systems in which the receive and transmit channels can not be tested at the same time because one channel, when processing signals, locks-out or disables the other channel from operating. Applicant's invention resides, in part, in the recognition that a signal applied to one channel will propagate through that channel with a given time delay. During a period of time TD, which is equal to the given time delay plus an optional additional period of time, the other channel is disabled. However, following the time delay TD, the disabling of the other channel is removed and it is rendered operable. Applicant's invention also resides in the recognition that if the output of one channel (e.g., the receive channel) were delayed for a period of time approximately equal to the time delay TD, the output of the one channel (e.g., the receive channel) could then be fed back (via a delay network) to the input of the second channel (e.g., the transmit channel) which would then be ready and able to process the “received” signal. The output of the second channel (e.g., the transmit channel) can then be compared with the signal applied to the input of the one channel (e.g., the receive channel) enabling the two channels (e.g., the receive and transmit channels) to be tested at the same time (except for the time delay) in response to one input test pattern. That is, the receive and transmit channel need not be tested separately.
Applicant's invention also resides in the connection of a delay network between the analog output of a receiver section and the analog input to a transmitter section. This delay network can be implemented using analog circuitry and/or digital circuitry. The delay network may be part of a tester which supplies digital test signals to the input of the receiver section and which senses the digital signals fed back from the output of the transmit section to compare the supplied signals versus the received signals. Thus, the use of a delay network enables the testing of a receive and transmit section at the same time.
In accordance with another embodiment of the invention, a tester can be used to concurrently test a receive section connected to its speaker together with a transmit section connected to its microphone. In this embodiment, the tester supplies a digital test pattern to the receiver which converts it to analog signals which are then supplied to the speaker which converts the analog signals to audio signals. The tester includes a section for converting the audio signals from the speaker to analog signals, for then converting the analog signals to digital signals and for then storing the digital signals. After a predetermined period, which corresponds to a desired delay, the tester reads the digital signals out of storage, converts them to analog signals, and then supplies the analog signals to the transmit section. The transmit section which is now enabled processes the received analog signals and produces corresponding digital signals which are supplied to the tester. The tester then compares the received delayed digital signals to the test pattern signal supplied to the receive section.
In another embodiment of the invention, a selectively enabled delay network may be inserted along the transmission path of the transmit section. The selectively enabled delay network is enabled only during testing; at other times, it appears as a short circuit along the transmission path. As a result, during testing, the output of the receive section can be connected directly to the input
Kobert Russell M.
Lucent Technologies - Inc.
Metjahic Safet
Schanzer Henry I
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