Look up table implementation of fast carry arithmetic and exclus

Details Look up table implementation of fast carry arithmetic and exclus Look up table implementation of fast carry arithmetic and exclus

1993-12-13

1996-01-02

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 750

Patent

active

054814863

ABSTRACT:
Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter. If desired, each logic module including such a look up table may further include logic circuitry for logically combining its normal output with the signal applied to its carry in input to facilitate the provision of wide fan in functions having more inputs than can be accepted by a single logic module.

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