Excavating
Patent
1994-03-07
1995-12-26
Nguyen, Hoa
Excavating
371 27, G01R 3128
Patent
active
054794145
ABSTRACT:
Algorithmically generated test patterns are structured for efficient test of "scan path" logic devices. A look ahead pattern generation and simulation scheme achieves a pre-specified fault coverage. The fault simulation engine picks one of two paths at the end of each Tester Loop (TL) simulation: (1) restore to the state just prior to the current simulated Tester Loop and advance the pattern generators one state if an ineffective Tester Loop was found or (2) advance the pattern generators one state (from the end of the Tester Loop) if an effective Tester Loop was encountered. This basic technique can be modified to support parallel fault simulation by defining the pattern generator state at the start of the next tester loop (TL) state (TL.sub.n+1) to be one state advanced from the pattern generator state at the START of TL.sub.n. The pattern generator state for the start of all future TLs can be determined and parallel fault simulation is supported.
REFERENCES:
Goel, "Lookahead Technique for Speeding up Fault Simulation for LSSD Logic Networks", IBM Tech. Disclosure Bulletin, vol. 21, No. 4 (Sep. 1978); pp. 1449-1450.
Hsiao, "Parallel Random Test Generation", IBM Technical Disclosure Bulletin, vol. 26, No. 2, Jul. 1983, pp. 775-776.
Keller Paul N.
Koprowski Timothy J.
International Business Machines - Corporation
Nguyen Hoa
Peterson Jr. Charles W.
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