Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1997-10-21
2001-03-27
Ngo, Chuong Dinh (Department: 2787)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06209014
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a Finite Impulse Response filtering, and more particularly to an adaptive weighting coefficient Finite Impulse Response filtering.
BACKGROUND OF THE INVENTION
A variety of digital techniques provide means of integrating filters capable of meeting high quality filter specifications. The performance of these filters typically equals and in particular cases exceeds performance available with passive Resistor-Inductor-Capacitive (RLC) filters.
Some truly integrated filters are discrete time filters in which a continuous time signal is sampled with a fixed periodicity and the analog amplitudes of the signal at the sample are linearly manipulated and transformed or digitally coded and processed before transformation. Filters which process sampled data linearly are classified as either Infinite Impulse Response (IIR) recursive filters or Finite Impulse Response (FIR) nonrecursive filters, depending upon whether the filter does or does not use recursion in internal loops when processing the samples.
While microprocessors are particularly suited for applications where speed and data handling size are not critical, they are not particularly well suitable for many data intensive applications. For example, medical imaging systems, speech recognition systems, and radar systems require that very large amounts of data be processed in real time. To increase their processing speed, a number of the systems utilize digital signal processors (DSP), which are optimized to process the sampled data at high rates. The repetitive nature of the signals allow the architecture of the digital signal processor to be optimized.
Referring to
FIG. 1
, there is shown a FIR filter
10
. The FIR filter
10
has a sampler
12
which samples the input signal V
in
(t) at a sampling frequency of ƒ
s
=1/T, where T is the sampling period. The output of the sampler
12
is coupled to M delay stages
14
in sequence. Each delay stage
14
delays the associated sample by the period T. The delayed sampled signal V
k
at each node k is coupled to a multiplier
16
where the signal is multiplied by the tap weighting coefficient h(k). The outputs of the multipliers
16
are coupled to a summer
18
which sums the products of the multiplication. The output of the summer
18
is coupled to provide the output of the filter V
out
(nT).
The FIR filter output V
out
(nT) is shown in Equation 1.
V
out
(
n
T
)
=
∑
k
=
1
M
h
(
k
)
V
k
(
n
T
)
Equation
1.
At t=nT the delay associated with node k is (k−1)T. Therefore, the signal at the node V
k
(nT) is shown in Equation 2 and the filter output is shown in Equation 3.
V
k
(
n
T
)
=
V
I
N
[
n
T
-
(
k
-
1
)
T
]
Equation
2.
V
out
(
n
T
)
=
∑
k
=
1
M
h
(
k
)
V
I
N
[
n
T
-
(
k
-
1
)
T
]
Equation
3.
This represents the linear convolution of the sequences h(k) and the sampled input signal. Where h(k) is the sequence of coefficients defining the impulse response of the filter, which is determined as the inverse Fourier transform of the desired filter response in the frequency domain, V
OUT
(nT) is the desired filter output in discrete time.
An adaptive FIR filter adapts the tap weighting coefficients h(k) of the multipliers
16
in response to the signal being processed. An adaptive Least Mean Square (LMS) algorithm consists of three steps: FIR filtering; prediction error computation; and filter coefficient update. In adaptive filtering by the LMS technique, the tap weighting coefficients h(k) are updated every sampling instant. In a programmable environment this poses a problem because of increased power consumption due to the large number of memory accesses. Some programmable systems may be able to reduce power by accessing two words at a time. This approach works only partially because most memory accesses are restricted to accessing double word at even address boundaries. Such as the words at the addresses 0, 2, 4, etc. In filtering applications this restriction is unacceptable if tap weights are to be updated every sample. If the tap weights are updated every second sample then it leads to errors and increased time to converge to the correct tap values. Furthermore, in even-aligned double-word memory fetch architectures, such as in a DSP having multiple Multiply Accumulate (MAC) units, the sample-by-sample LMS update algorithm tends to be cumbersome due to the memory misalignment of every odd sample.
Therefore, there is a need to update tap weights without discarding alternate input samples while only doing double word access from memory, which reduces computation time and power consumption without sacrificing performance.
SUMMARY OF THE INVENTION
In accordance with the present invention, an apparatus and a technique for adapting a plurality of tap weights in an adaptive filter is described. The plurality of tap weights are adapted utilizing every other time count using all samples of a sequence of samples. The apparatus comprises a sampler circuit for sampling an input signal producing a sequence of samples; a tap weight processor for generating the plurality of tap weights coupled to the sampler circuit; wherein the plurality of tap weights are adapted utilizing every other sample of the sequence of samples. A method in accordance with the present invention is also described.
REFERENCES:
patent: 5216629 (1993-06-01), Gurcan et al.
patent: 5327459 (1994-07-01), Hara et al.
patent: 5414732 (1995-05-01), Kaufman
patent: 5734598 (1998-03-01), Abbott et al.
Pipeline Interleaving and Parallelism in Recursive Digital Filter-Part I: Pipelining Using Scattered Look-Ahead and Decomposition, Author-Keshab K. Parhi and David G. Messerschmitt, 1989 IEEE Trans.
Pipeline Interleaving and Parallelism in Recursive Digital Filter-Part II:, Author-Keshab K. Parhi et al., 1989 IEEE Trans.
Gibbons Del Deo Dolan Griffinger & Vecchione
Lucent Technologies - Inc.
Ngo Chuong Dinh
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