Look ahead encoder/decoder architecture

Details Look ahead encoder/decoder architecture Look ahead encoder/decoder architecture

1999-12-15

2003-08-12

Vanderpuye, Ken (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C341S058000

Reexamination Certificate

active

06606328

ABSTRACT:

FIELD
The present invention pertains to encoders and decoders. More particularly, the present invention pertains to cascaded, look-ahead encoder/decoder architecture, and especially 8-bit/10bit encoder/decoder architecture.
BACKGROUND
Communication networks often utilize 8-bit/10-bit (“8B/10B”) encoders and decoders to improve reliability. An 8B/10B encoder encodes received eight bit bytes of binary data into ten bit bytes plus a disparity bit which indicates whether there is a difference between the number of ones and the number of zeros in the ten bit byte. The ten bit byte includes eight data bits and two check bits. Conversely, an 8B/10B decoder converts ten bit bytes of binary data into eight bit bytes plus a disparity bit. 8B/10B encoders and decoders are described, for example, in U.S. Pat. No. 4,486,739 and in the article “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code,” by A. X. Widmer and T. A. Franaszek,
IBM Journal of Research and Development
, Volume 25, No. 5(September 1983), pages 440-451.
Improved communication capabilities have resulted in increased speed at which data can be transmitted. Basic 8B/10B encoders and decoders are limited in speed of operation and so present a potential limitation to data transmissions speed. While it might appear that speed of operation can be improved by cascading two 8B/10B encoders or two 8B/10B decoders, cascading, in fact, can not improve the speed because before the second encoder or decoder can commence processing, the disparity of the character encoded or decoded by the first encoder or decoder must be determined.
SUMMARY
The present invention is an 8B/10B encoder network including a number of pairs of 8B/10B encoders. One encoder of each encoder pair receives a positive disparity input signal, while the other encoder of each pair receives a negative disparity input signal. A data source provides successive eight bit input bytes of binary data cyclically to each encoder pair for simultaneous encoding by each encoder of the pair. A multiplexer is provided for each encoder pair to multiplex the ten bit output bytes and disparity signals provided by the two encoders of the pair in accordance with a control signal applied to the multiplexer. Each multiplexer applies its disparity output signal as the control signal of another of the multiplexers so that the multiplexers are connected in a ring. Application of the disparity output signal from one of the multiplexers to the control input of the next multiplexer in the ring is delayed to provide proper timing.
In a further aspect, the present invention is a similarly constructed 8B/10B decoder network.


REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 6111528 (2000-08-01), Bagley
patent: 6438728 (2002-08-01), Susnow
A. Widmer et al., “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”,IBM J. Res. Develop.,Vo. 27, No. 5, Sep. 1983, pp. 441-451.

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