Look-ahead enabling charge pump in phase-locked loop circuits

Details Look-ahead enabling charge pump in phase-locked loop circuits Look-ahead enabling charge pump in phase-locked loop circuits

2000-03-23

2001-08-21

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S148000, C327S162000, C327S536000, C331SDIG002, C375S374000

Reexamination Certificate

active

06278304

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to phase-locked loops. In particular, the invention relates to the charge pump in phase-locked loop circuits.
2. Description of Related Art
A phase-locked loop (PLL) circuit generates an output signal based on a control voltage representing the phase difference between a reference phase signal and a feedback signal. A charge pump circuit pumps current to be converted into the control voltage.
The charge pump circuit is normally biased by a charge pump bias circuit. The charge pump bias circuit provides a reference signal to establish the amount of current to be pumped. In traditional PLL circuits, the charge pump circuit continuously consumes power whether or not the PLL circuit is locked. Between pulses in the output signal, the charge pump circuit is idle, but still draws current, wasting power.
Therefore there is a need in the technology to provide a simple and efficient method to control a charge pump in phase-locked loop circuits.
SUMMARY
The present invention is a method and apparatus for controlling a charge pump bias circuit in a phase-locked loop (PLL) circuit. The charge pump bias circuit biases a charge pump circuit. A digital phase detector generates direction control signals based on reference and pre-scale count signals from reference and pre-scale counting circuits, respectively. The direction control signals control the direction of current pumped by the charge pump circuit. A charge pump enable generator generates an enable signal based on look-ahead reference and pre-scale count signals from the reference and pre-scale counting circuits, respectively. The look-ahead reference and pre-scale count signals are generated before the corresponding reference and pre-scale count signals by a predetermined time interval. The enable signal turns on the bias circuit just before the charge pump circuit pumps current and powers down the charge pump bias circuit just after the charge pump circuit pumps the current.
In one embodiment, the digital phase detector comprises first and second synchronizers and a reset generator; and the charge pump enable generator comprises a look-ahead circuit and an enable gating circuit. The first synchronizer generates the up direction signal based on a reference count signal from the reference counting circuit. A second synchronizer generates the down direction signal based on a pre-scale count signal from the pre-scale counting circuit. A reset generator generates a reset signal, the reset signal resetting the first and second synchronizers. The look-ahead circuit generates a look-ahead signal at a time interval before the direction control signals are generated. The enable gating circuit gates the look-ahead signal with a lock detection signal, the gated look-ahead signal corresponding to the enable signal.


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