Look-ahead carry adder circuit

Details Look-ahead carry adder circuit Look-ahead carry adder circuit

2008-01-29

2008-01-29

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07325025

ABSTRACT:
A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of three stages. In an embodiment, the look-ahead carry adder has only one critical path. In a further embodiment, the load on the critical path is minimized by using buffers.

REFERENCES:
patent: 4118786 (1978-10-01), Levine et al.
patent: 4323981 (1982-04-01), Nakamura
patent: 4570084 (1986-02-01), Griffin et al.
patent: 4573137 (1986-02-01), Ohhashi
patent: 4584661 (1986-04-01), Grundland
patent: 4623982 (1986-11-01), Ware
patent: 4737926 (1988-04-01), Vo et al.
patent: 5117386 (1992-05-01), Persoon et al.
patent: 5146424 (1992-09-01), Peterson et al.
patent: 5278783 (1994-01-01), Edmondson
patent: 5568069 (1996-10-01), Chow
patent: 5777491 (1998-07-01), Hwang
patent: 5896308 (1999-04-01), Gonfaus et al.
patent: 5943251 (1999-08-01), Jiang et al.
patent: 5977789 (1999-11-01), Gayles
patent: 6028454 (2000-02-01), Elmasry et al.
patent: 6208907 (2001-03-01), Durham et al.
patent: 5-259893 (1993-10-01), None
Related U.S. Appl. No. 09/956,903, filed Sep. 21, 2001.
Related U.S. Appl. No. 09/892,565, filed Jun. 28, 2001.
Related U.S. Appl. No. 09/893,868, filed Jun. 29, 2001.
Yee et al, “Clock-Delayed Domino for Dynamic Circuit Design”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, No. 4, Aug. 2000, pp. 425-430.
Yee et al, “Clock-Delayed Domino for Adder and Combinational Logic Design”, IEEE, 1063-6404/96, pp. 332-337, 1996.
Jung, Perepelitsa, Sobelman, “Time Borrowing in High-Speed Functional Units Using Skew-Tolerant Domino Circuits,” Proceedings, IEEE International Symposium on Circuits and Systems, pp. V-641-V-644, 2000.
Presentation by Carl Sechen dated Mar. 17, 2000.
Taub,Digital Circuits and Microprocessors, pp. 205-212, Mc-Graw-Hill, 1982.

Affiliated with

Also associated with

Rating

Look-ahead carry adder circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Look-ahead carry adder circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Look-ahead carry adder circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2788751