Long period pseudo random number sequence generator

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3647461, G06F 102

Patent

active

048902527

ABSTRACT:
A circuit for generating a sequence of pseudo random numbers, {A.sub.k }. There is an exponentiator (30') in GF(2.sup.m) for the normal basis representation of elements in a finite field GF(2.sup.m) each represented by m binary digits and having two inputs and an output from which the sequence {A.sub.k } of pseudo random numbers is taken. One of the two inputs is connected to receive the outputs {E.sub.k } of maximal length shift register of n stages. There is a switch (32) having a pair of inputs and an output. The switch (32) output is connected to the other of the two inputs of the exponentiator (30'). One of the switch (32) inputs is connected for initially receiving a primitive element A.sub.0 in GF(2.sup.m). Finally, there is a delay circuit (34) having an input and an output. The delay circuit (34) output is connected to the other of the switch (32) inputs and the delay circuit (34) input is connected to the output of the exponentiator (30') whereby after the exponentiator (30') initially receives the primitive element A.sub.0 in GF(2.sup.m) through the switch (32), the switch (32) can be switched to cause the exponentiator (30') to receive as its input a delayed output A.sub.k-1 from the exponentiator (30') thereby generating {A.sub.k } continuously at the output of the exponentiator (30'). The exponentiator (30') in GF(2.sup.m) is novel and comprises a cyclic-shift circuit; a Massey-Omura multiplier; and, a control logic circuit all operably connected together to perform the function U.sub.i =.sub..alpha. 2.sup.i (for n.sub.i =1) or 1 (for n.sub.i =0).

REFERENCES:
patent: 3614400 (1971-10-01), Farnett et al.
patent: 4251875 (1981-02-01), Marver et al.
patent: 4587627 (1986-05-01), Omura et al.
Wang et al, "VLSI Architectures for Computing Multiplications and Inverses in GF(2.sup.m)", IEEE Trans. on Comp., vol. C-34, No. 8, Aug. 1985, pp. 709-717.

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