Long latency interrupt handling and input/output write posting

Details Long latency interrupt handling and input/output write posting Long latency interrupt handling and input/output write posting

1996-07-19

1999-08-24

Lall, Parshotam S.

Cryptography

Key management

Having particular key generator

395868, 395734, 395733, 395736, 395725, 395425, 395750, 380 4, G06F 946

Patent

active

059435003

ABSTRACT:
An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller. The back-to-back wait requirement prevents false interrupts from being generated in the event that the cleared interrupt may have missed its transmission window over the current interrupt serial bus cycle, or the event that the cleared interrupt was delayed by any interrupt serial bus transmission latencies.

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