Long-integer multiplier

Details Long-integer multiplier Long-integer multiplier

2004-07-22

2009-12-01

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07627625

ABSTRACT:
An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level and its lowest (output) level.

REFERENCES:
patent: 4791601 (1988-12-01), Tanaka
patent: 5787029 (1998-07-01), de Angel
patent: 6421699 (2002-07-01), Dhong et al.
patent: WO 94/12928 (1994-06-01), None
L. Dadda: “Some Schemes for Parallel Multipiers”; Alta Frequenza ; vol. 34, No. 5; May 1965 pp. 349-356.
L. Dadda: “Some Schemes for Fast Serial Input Multipiers”; Proceddings of 6thSymposium on Computer Arithmetic Jun. 20-22, 1983; Aarhus University; Aarhus Denmark; Jun. 22, 1983; pp. 52-59.

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