Logically disconnectable virtual-to-physical address translation

Details Logically disconnectable virtual-to-physical address translation Logically disconnectable virtual-to-physical address translation

1994-09-07

1996-10-08

Bowler, Alyssa H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395417, 395750, 365 49, 364253, 3642564, 3642733, 364DIG1, G06F 132

Patent

active

055640524

ABSTRACT:
A method and structure for logically disconnecting an on-chip virtual-to-physical address translation unit from a microprocessor by holding the dynamic circuits of the translation unit in precharged state. In one embodiment, the method and structure provide a fixed remapping for the virtual address. A powering down of the translation unit effects power savings when the translation unit is not required.

REFERENCES:
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patent: 5107417 (1992-04-01), Yokoyama
patent: 5237671 (1993-08-01), Freitas et al.
patent: 5325507 (1994-06-01), Freitas et al.

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