Logical transform image processor

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Details

364521, 382 27, 382 41, G06F 1640, G06F 956

Patent

active

046672958

ABSTRACT:
A minicomputer provides signals representative of an image to three memory units via a sixteen bit data bus. Signals representative of sixteen central pixels of the image and neighbors thereof are provided from the memory units to a tessellation memory. In response to the central pixels and their neighbors forming a predetermined pattern, signals representative of the central pixels may be altered, whereby the central pixels are processed simultaneously. Signals representative of the processed central pixels are provided to the minicomputer via the data bus.

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patent: 4393453 (1983-07-01), Nakano
patent: 4395698 (1983-07-01), Sternberg et al.
patent: 4464789 (1984-08-01), Sternberg
patent: 4484349 (1984-11-01), McCubbrey

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