Logical-to-real address translation based on selective use of fi

Details Logical-to-real address translation based on selective use of fi Logical-to-real address translation based on selective use of fi

1993-07-21

1996-02-06

Whitfield, Michael A.

Boots, shoes, and leggings

364DIG1, 395417, G06F 1210

Patent

active

054902592

ABSTRACT:
Under such a condition between outputs of AND circuits for outputting All "0" when one of zero detecting circuits of two register identifiers within an instruction register detects "0", instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.

REFERENCES:
patent: 5148538 (1992-09-01), Celtruda et al.

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