Logical synthesizing device, logical synthesizing method, and se

Details Logical synthesizing device, logical synthesizing method, and se Logical synthesizing device, logical synthesizing method, and se

1995-09-26

1998-02-03

Teska, Kevin J.

Boots, shoes, and leggings

371 221, G06F 1750, G01R 3128

Patent

active

057151717

ABSTRACT:
A logical synthesizing device and logical synthesizing method capable of generating a net list from a feedback loop added flip-flop excellent in layout efficiency. In a cell library, cells of feedback loop added flip-flop are newly registered together with existing various cells. The feedback loop portion of this feedback loop added flip-flop is formed in an optimum layout composition in consideration of the setup time and hold time. A logical synthesizing section, using the cells registered in the cell library, generates a net list for realizing a logical function description, and outputs to a test design section At this time, the feedback loop forming portion in the input and output of the flip-flop generates the net list by using the feedback loop added flip-flop.

REFERENCES:
patent: 4831543 (1989-05-01), Mastellone
patent: 5519627 (1996-05-01), Mahmood et al.
patent: 5550839 (1996-08-01), Buch et al.
Brglez et al., "Synergy of Synthesis and Test", 1989 IEEE 8th Biennial Univ./Gov't./Industry Symposium, pp. 240-245.
Cheng et al., "A Partial Scan method for Sequential Circuits w/Feedback," IEEE Trans. on Computers, vol. 39, No. 4, Apr. 1990, pp. 544-548.
Courjon, "Scan Design in the Philips ASIC Test Environment," Euro ASIC '90, pp. 370-375.

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