Logical simulator with event load measuring and model recreating

Details Logical simulator with event load measuring and model recreating Logical simulator with event load measuring and model recreating

1996-07-15

1998-06-16

Teska, Kevin J.

Boots, shoes, and leggings

395500, G06F 1516

Patent

active

057681600

ABSTRACT:
A logical simulator that creates a logical simulation model that can equally distribute the load to each processing element and certainly suppress a decrease in a parallel processing efficiency due to each processing element waiting for its synchronous operation, thus increasing the speed of the logical simulation. The logical simulator includes a load measuring unit for measuring the load of each of processing elements at a logical simulation execution time, and a load data file for holding as load data the result measured by the load measuring unit. The model creating unit creates a logical simulation model with a small load bias of each of the processing elements at the logical simulation execution time, based on the measured result from the load measuring unit. The logical simulator is applicable to check for the correctness in design before fabricating digital equipment such as a digital computer formed of logical circuits.

REFERENCES:
patent: 4306286 (1981-12-01), Cocke et al.
patent: 5442772 (1995-08-01), Childs
"Partitioning Strategics Within a Distributed Multilevel Logic Simulator Including Dynamic Repartition" Negoglou Simic, 1993 IEEE pp. 96-101.
"Digtributed Logic Circuit Simulation in a Network Workstations" Luben beianor, 1995 IEEE, pp. 304-310.
"DiPacs, A New Concept for Parallal Circuit Simulation" Volkhard Klinger. 1995 IEEE, pp. 32-41.

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