Logical separation and accessing of descriptor memories

Details Logical separation and accessing of descriptor memories Logical separation and accessing of descriptor memories

2007-05-08

2007-05-08

Pham, Chi (Department: 2616)

Multiplex communications

Pathfinding or routing

Combined circuit switching and packet switching

C370S392000, C370S353000, C370S401000, C370S389000, C370S474000, C709S236000, C709S230000

Reexamination Certificate

active

10102933

ABSTRACT:
A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the number of distinct memory portions. The packet header processing unit is configured to retrieve the different types of descriptor information from the number of distinct memory portions and to generate header information from the different types of descriptor information.

REFERENCES:
patent: 5608786 (1997-03-01), Gordon
patent: 5938736 (1999-08-01), Muller et al.
patent: 6067300 (2000-05-01), Baumert et al.
patent: 6172981 (2001-01-01), Cox et al.
patent: 6275508 (2001-08-01), Aggarwal et al.
patent: 6289023 (2001-09-01), Dowling et al.
patent: 6442669 (2002-08-01), Wright et al.
patent: 6560228 (2003-05-01), Kingsley
patent: 6629141 (2003-09-01), Elzur et al.
patent: 6671722 (2003-12-01), Stachura et al.
patent: 6721316 (2004-04-01), Epps et al.
patent: 6807581 (2004-10-01), Starr et al.
patent: 6920133 (2005-07-01), Boodaghians
patent: 6970468 (2005-11-01), Doidge et al.
patent: 2002/0016905 (2002-02-01), Kojima et al.
patent: 2002/0064130 (2002-05-01), Siu et al.
patent: 2002/0116595 (2002-08-01), Morton
patent: 2003/0076850 (2003-04-01), Jason, Jr.
patent: 2003/0097481 (2003-05-01), Richter
patent: 2003/0172177 (2003-09-01), Kersley et al.
patent: 2004/0085962 (2004-05-01), Sugai et al.
patent: 2004/0228339 (2004-11-01), Gallo et al.
Co-pending U.S. Appl. No. 10/102,960; filed on Mar. 22, 2002; entitled: “Parallel Layer 2 and Layer 3 Processing Components in a Network Router”; 41 page specification; 15 sheets of drawings.
Co-pending U.S. Appl. No. 10/102,932; filed on Mar. 22, 2002; entitled: “Optimized Buffer Loading for Packet Header Processing”; 44 page specification; 15 sheets of drawings.
Co-pending U.S. Appl. No. 10/102,961; filed on Mar. 22, 2002; entitled: “Mailbox Registers for Synchronizing Header Processing Execution”; 42 page specification; 15 sheets of drawings.
Co-pending U.S. Appl. No. 10/102,931; filed on Mar. 22, 2002; entitled: “Dedicated Processing Resources for Packet Header Generation”; 44 page specification; 15 sheets of drawings.
Co-pending U.S. Appl. No. 10/102,951; filed on Mar. 22, 2002; entitled: “Systems and Methods for Handling Packet Fragmentation”; 35 page specification; 15 sheet of drawings.
Co-pending U.S. Appl. No. 10/102,958; filed on Mar. 22, 2002; entitled: “On The Fly Header Checksum Processing Using Dedicated Logic”; 35 page specification; 15 sheets of drawings.

Affiliated with

Also associated with

Rating

Logical separation and accessing of descriptor memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logical separation and accessing of descriptor memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logical separation and accessing of descriptor memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3800364