Logical OR circuit for programmed logic arrays

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307207, 307218, 307251, 364716, H03K 1908, H03K 1930, H03K 1704, G06F 900

Patent

active

041236696

ABSTRACT:
An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.

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