Logical comparison circuit

Details Logical comparison circuit Logical comparison circuit

1991-07-15

1994-11-15

Baker, Stephen M.

Excavating

3401462, G01R 3128

Patent

active

053655273

ABSTRACT:
A sample data signal obtained by sampling the response output from an IC under test is converted by an interleave circuit into n trains of low-speed signals each having an n-fold period. The trains of low-speed signals are strobed out by n-phase pulses generated by a multi-phase pulse generator from a system clock synchronized with an expected value pattern signal. The strobed-out signals are combined into a data signal of the original frequency synchronized with the expected value pattern signal. The data signal synchronized with the expected value pattern signal is compared by a comparator circuit with the expected value pattern signal.

REFERENCES:
patent: 4270116 (1981-05-01), Ichimaya et al.

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