Logical check apparatus and method for semiconductor circuits an

Details Logical check apparatus and method for semiconductor circuits an Logical check apparatus and method for semiconductor circuits an

1996-12-04

1998-10-27

Tu, Trinh L.

Excavating

39518313, 364578, G11C 2900, G06F 1100, G06G 748

Patent

active

058286730

ABSTRACT:
A semiconductor circuit logical check apparatus including a unit for extracting information about laser trimming fuse elements based on layout data and logic-circuit diagram data of a semiconductor circuit, a unit for generating a command sequence indicating that some of the laser trimming fuse elements are broken on the basis of the extracted laser trimming fuse element information, a unit for generating error bit memory cell array models from memory cell array models, and a unit for executing, on a semiconductor circuit model, logic simulation on the basis of the command sequence.

REFERENCES:
patent: 5381345 (1995-01-01), Takegami et al.
patent: 5446674 (1995-08-01), Ikeda et al.
patent: 5490095 (1996-02-01), Shimada et al.
patent: 5613062 (1997-03-01), Hasebe et al.

Affiliated with

Also associated with

Rating

Logical check apparatus and method for semiconductor circuits an does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logical check apparatus and method for semiconductor circuits an, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logical check apparatus and method for semiconductor circuits an will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1619877