Logical bus structure including plural physical busses for a mul

Details Logical bus structure including plural physical busses for a mul Logical bus structure including plural physical busses for a mul

1996-11-27

1999-03-30

An, Meng-Ai T.

395311, 395729, G06F 1300

Patent

active

058899693

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The invention is concerned with an improved multiple bus concept for multiprocessor computer systems, which predominantly comprise a multiple level cache structure. In particular this concept provides an improved bus switching unit and a method for near end signal reception in case of more processors electrically interconnected via such a bus system.


BACKGROUND OF THE INVENTION

The bus structure in a multiprocessor computer system has a significant impact on the overall performance, the functionality and the granularity of the system. One of the most important key characteristics for an efficient bus is its bandwidth which describes the ability of the bus to match with the processors speed and a variable number of processors. It depends on the bus width, the efficient usage of the bus by the bus protocol and the bus cycle time.
The bus width is limited by physical constraints of the package as there are chip pads, module pins or wireability of cards and boards. In prior art bus systems therefore either one large or a set of smaller busses is constructed.
In another prior art approaches a smart bus protocol allows bus interleaving between processors to fill the time gap on the bus caused by the access time of the addressed memory bank. "Bus interleaving" is a known method to use wait cycles on a bus to issue a command to other memory banks. It allows several memory banks per bus to be operated simultaneously in order to increase the bus- and memory bandwidth.
The bus cycle time is the main contributor to the bus bandwidth. An efficient bus structure has to provide excellent electrical characteristics to match the processor and the bus cycle time as close as possible. For example, a simple structure which connects processors like a laundry line limits the cycle time and the number of processors by its poor electrical characteristics. In contrast, a much more complex structure provides point to point busses between each processor and a central switch unit. One or several memory banks are connected to that unit. That structure allows a short bus cycle, but requires an extensive wiring. For the packaging, a central switch unit also requires a very high pin count, since all busses are routed to the switch.
In addition, in prior art systems the performance of bus structures is improved by concepts for bus arbitration which may either be implemented as a distributed or a central arbitration function. The central arbitration concept is based on an additional hardware component, a controller, like a central bus switch. It receives all bus requests, performs the arbitration and delivers the grant to the requesting unit in the next cycle.
The distributed approach requires more wiring, because all request lines have to be wired to all bus participants. But its advantage is that the arbitration can be fulfilled within one cycle, since only one off-chip network is in the path, compared with the a central arbitration. The complete path consists of an off-chip network, i.e. the request lines, and the arbitration logic. If this limits the bus cycle time, then a two cycle central bus arbitration will become the preferred solution.
A further key characteristic for an efficient bus structure is the provisions which provides for data consistency assurance in a multiple cache processor structure. A known simple concept is the so called bus snooping. Hereby each processor monitors the bus operations of all other processors to keep track on the status of its cache lines. The status may be "modified", "exclusive", "shared" or "invalid". The required actions are a line invalidation or a cast-out of modified data with or without updating the memory. A cast-out of modified data means that a PU is no longer the exclusive owner of the line. All those operations are initiated and controlled by the individual processors.
But this simple concept has its limits, if there is more than one bus in the structure, as in a system with a central switch. Hereby data consistency has to be controlled by the central switch.

REFERENCES:
patent: 4807184 (1989-02-01), Shelor
patent: 5594876 (1997-01-01), Getzlaff et al.

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