Logical block for a Viterbi decoder

Details Logical block for a Viterbi decoder Logical block for a Viterbi decoder

1996-10-03

1999-03-23

Chin, Stephen

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

371 436, 371 437, H03M 1312

Patent

active

058870369

ABSTRACT:
A logical block is disclosed for decoding a data sequence encoded by a convolutional code, in which a given number of states are to be evaluated. These given states are assigned the given number of state memories which store an associated path and an accumulated distance value. The given number of state memories are associated with parallel processing blocks which each have, as the smallest group to be processed in parallel, two state memories to be read from first and second parallel processing blocks, and two state memories to be written into third and fourth parallel processing blocks. Optimum memory organization permits simple parallel processing and reduction in circuit complexity.

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patent: 5541955 (1996-07-01), Jacobsmeyer
Convolutional Codes and Their Performace in Communication Systems, IEEE Transactions on Communications Technology, vol., COM-19, No. 5, Andrew J. Viterbi, Oct. 1971, pp. 751-772.

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