Logical address generating device for an instruction specifying

Details Logical address generating device for an instruction specifying Logical address generating device for an instruction specifying

1989-09-26

1992-08-04

Popek, Joseph A.

395425, G06F 926, G06F 900

Patent

active

051366991

ABSTRACT:
On generating a logical address from first through third words where the third word has a predetermined word length and the first and the second words are longer, a lower sum is calculated together with a carry by using the third word and first and second lower parts which are selected from the first and the second words to have predetermined word length. The carry is either a binary zero or a binary one bit. Necessity or lack of necessity for addition of first and second higher parts and the carry is decided by using the second higher part and the carry. When the addition is unnecessary, the first higher part and the lower sum are concatenated into the logical address. If the addition is necessary, a higher sum of the first and second higher parts and the carry is calculated and concentrated with the lower sum into the logical address. The addition is unnecessary either when the second higher part consists of binary zero bits and the carry is the binary zero bit or when the second highest part consists of binary one bits and the carry is the binary one bit.

REFERENCES:
patent: 3938096 (1976-02-01), Brown et al.
patent: 3949378 (1976-04-01), Crabb et al.
patent: 3976978 (1976-08-01), Patterson et al.
patent: 4206503 (1980-06-01), Woods et al.
patent: 4240139 (1980-12-01), Fukuda et al.
patent: 4361868 (1982-11-01), Kaplinsky
patent: 4385352 (1983-05-01), Bienvenu

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