Logical address bus architecture for multiple processor systems

Details Logical address bus architecture for multiple processor systems Logical address bus architecture for multiple processor systems

1995-12-18

1998-05-19

Sheikh, Ayaz R.

395728, 395731, 395293, 39520057, 39520058, 39520067, 39520079, G06F 946, G06F 1314

Patent

active

057548650

ABSTRACT:
A logical bus architecture implements by active devices the functions performed by a physical address/command bus in the context of a multiple processing unit computer system. The logical bus eliminates the electrical loading, and associated frequency limitations, characterizing physical address/command buses as the number of system resources, processing units, connected to the bus increase. Address/command buses from the processing units are individually or in groups connected to ports of an address rebroadcast device. The device also receives bus master information from the computer system arbiter. Since the arbiter information is available before the actual transmission of signals over the address/command buses of the various processing units, bidirectional signal paths in the address rebroadcast device are selectively configured to match the master-slave signal flow between processing units as defined by the arbiter. Address/command signals are received from the master processing unit at one port and appropriately rebroadcast through the other ports to the other processing units with no more than gate propagation delays. Reconfiguration of the port directions in the address rebroadcast device is accomplished with each designation of a new bus master by the arbiter. Not only does the address rebroadcast device eliminate bus loading, but it also facilitates the selective isolation of processing units by port for fault testing and the like.

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