Logic verification method

Details Logic verification method Logic verification method

1994-03-21

1996-04-02

Beausoliel, Jr., Robert W.

G06F 1100

Patent

active

055048625

ABSTRACT:
A logic verification method for simulating a logic circuit model by using the instruction interpreter, connected to the first and second files, for executing an executable program, includes the steps of: outputting to the second file first status information after the executable program loaded from the first file and already compiled has been executed to an inputted first location; outputting to the second file second status information after the executable program loaded from the first file has been executed to an inputted second location in the instruction interpreter; setting the first status information to the memory unit of the logic circuit model; and outputting to the display, together with the second status information, third status information after the executable program has been executed from the fist location to the second location in the logic circuit model. The first and second locations are assigned by the operator to save the executable program and set an interruption instruction. When a simulation error has occurred, it is possible to alter the first status information and make the executable program to execute and the other portion of the executable program to execute without recompiling.

REFERENCES:
patent: 4551837 (1985-11-01), Goegeiein et al.
patent: 4937770 (1990-06-01), Samuels et al.
patent: 5051938 (1991-09-01), Hyduke
patent: 5095454 (1992-03-01), Huang
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5377122 (1994-12-01), Werner et al.

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