Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2007-01-30
2007-01-30
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S014000, C703S028000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
09347690
ABSTRACT:
A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.
REFERENCES:
patent: 5260949 (1993-11-01), Hashizume et al.
patent: 5469366 (1995-11-01), Yang et al.
patent: 5787009 (1998-07-01), Pedersen
patent: 5828579 (1998-10-01), Beausang
patent: 5903466 (1999-05-01), Beausang et al.
patent: 5949692 (1999-09-01), Beausang et al.
patent: 5956256 (1999-09-01), Rezek et al.
K. Hering, R. Haupt, Th. Villman, “Hierarchical Strategy of Model Partitioning for VLSI-Design Using an Improved Mixture of Experts Approach.” Parallel and Distrubted Simulation, 1996. Pads 96. Proceedings. Tenth Workshop on, 1996 pp. 106-113.
M. L. Bailey, J. V. Briner, Jr., R. D. Chamberlain, “Parallel Logic Simulation of VLSI Systems,” ACM Computing Surveys, vol. 26, No. 3, Sep. 1994.
Thomas Hollstein, Jurgen Becker, Andreas Kirschbaum, Manfred Glesner, “HiPART: A New Hierarchical Semi-Interactive HW-/SW Partitioning Approach with Fast Debugging for Real-Time Embedded Systems”, Proceedings, Mar. 1998, 5 pages.
Naraig Manjikian, Wayne M. Loucks, “High Performance parallel logic simulations on a network of workstations”, ISSN:0163-6103, ACM 1993, pp. 76-84.
Bryant, R.E., et al., “COSMOS: A Compiled Simulator for MOS Circuits”,Proceedings of the 24th ACM/IEEE Design Automation Conference, Miami Beach, FL, pp. 9-16, (1987).
Casas, J., et al., “Logic Verification of Very Large Circuits Using Shark”,Proceedings of the Twelfh International Conference on VLSI Design, Goa, India, pp. 310-317, (Jan. 7-10, 1999).
Manjikian, N., et al., “High Performance Parallel Logic Simulation on a Network of Workstations”,Proceedings of the 7th Workshop on Parallel and Distributed Simulation(PADS), San Diego, CA, pp. 76-84 (May 16-19, 1993).
Casas Jeremy S.
Joshi Mandar S.
Khaira Manpreet S.
Otto Steve W.
Seligman Erik M.
Craig Dwin McTaggart
Intel Corporation
Rodriguez Paul
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Logic verification in large systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Logic verification in large systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic verification in large systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3790274