Logic translation method for increasing simulation emulation eff

Details Logic translation method for increasing simulation emulation eff Logic translation method for increasing simulation emulation eff

1996-06-13

1998-06-02

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 9455

Patent

active

057614881

ABSTRACT:
A method of speeding up computer simulation/emulation of circuit logic designs. The method converts an original circuit logic design (intended for hardware packaging) to a different circuit form before starting computer simulation/emulation. The converted circuit form provides the same simulation/emulation results as would have been obtained with the original logic circuit. The method operates with multi-phase logic designs comprised of gate circuits using multi-phase clocking of the type commonly packaged in semiconductor chips. The method converts such multi-phase logic designs into a single-phase circuit form, which is presented to the computer for simulation/emulation that provides the same results as the multi-phase logic design but at a much faster speed. The method is presented with a multi-phase logic design containing flip-flops as the internal storage circuits. The method effectively retains the storage circuits found in a multi-phase logic design and replicates its logic blocks providing multiple phase outputs. Then the storage circuits are reconnected to the original and replicated logic blocks in a manner that enables a single clock cycle to operate the converted logic design to simulate/emulate the same results in the storage circuits, as if the original multi-phase logic design were being simulated or emulated, but at a much faster speed.

REFERENCES:
patent: 4527249 (1985-07-01), Van Brunt
patent: 4769817 (1988-09-01), Krohn et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4852093 (1989-07-01), Koeppe
patent: 4970405 (1990-11-01), Hagiwara
patent: 5014234 (1991-05-01), Edwards, Jr.
patent: 5081601 (1992-01-01), Eirikasson
patent: 5302866 (1994-04-01), Chiang et al.
patent: 5355321 (1994-10-01), Grodstein et al.
patent: 5389838 (1995-02-01), Orengo
patent: 5394443 (1995-02-01), Byers et al.
Kahle, JA et al., "Single-Latch Element Modeling Technique", IBM Technical Disclosure Bulletin, vol. 36, No. 8, Aug. 1993, pp. 355-356.

Affiliated with

Also associated with

Rating

Logic translation method for increasing simulation emulation eff does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic translation method for increasing simulation emulation eff, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic translation method for increasing simulation emulation eff will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1472399