Multiplex communications – Wide area network – Packet switching
Patent
1980-05-05
1982-10-12
Orsino, Jr., Joseph A.
Multiplex communications
Wide area network
Packet switching
364200, H04Q 1104
Patent
active
043542620
ABSTRACT:
A control logic system comprising at least one sub-system including a master processor, two slave processors and an interchange memory which exchanges information between the master processor and the slave processors. The slave processors access a common memory via an interprocessor interface.
REFERENCES:
patent: 3516074 (1970-06-01), Enomoto
patent: 3999162 (1976-12-01), Leroy
patent: 4150335 (1979-04-01), Cooperman
Guezou Jean
LeDieu Bernard
Martin Jean-Pierre
Compagnie Industrielle des Telecommunications Cit-Alcatel
Orsino Jr. Joseph A.
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