Logic synthesis of multi-level domino asynchronous pipelines

Details Logic synthesis of multi-level domino asynchronous pipelines Logic synthesis of multi-level domino asynchronous pipelines

2009-05-04

2011-11-01

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S114000, C716S132000

Reexamination Certificate

active

08051396

ABSTRACT:
Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

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