Logic synthesis method, semiconductor integrated circuit and ari

Details Logic synthesis method, semiconductor integrated circuit and ari Logic synthesis method, semiconductor integrated circuit and ari

1998-10-15

1999-11-02

Teska, Kevin J.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With large area flexible electrodes in press contact with...

39550003, 257299, 257500, 326 80, G06F 1750, G06F 752, H03K 190175

Patent

active

059785730

ABSTRACT:
A top-down design technique is used to design a semiconductor integrated circuit having a plurality of registers and a plurality of combinational circuits each of which is connected between the registers. When a semiconductor integrated circuit is logic-synthesized from a register transistor level, a front section of a critical path-containing combinational circuit is driven by a high voltage from a high-voltage source while the remaining section and other combinational circuits with no critical path are driven by a low voltage from a low-voltage source. A level shifter is placed at the stage before the critical path-containing combinational circuit. The level shifter converts a low-voltage signal into a high-voltage one. This invention facilitates logic synthesis of a low-power semiconductor circuit without increasing the maximum signal propagation delay of the critical path and without having to provide a level shifter in a combinational circuit.

REFERENCES:
patent: 3950636 (1976-04-01), Dao
patent: 4713796 (1987-12-01), Ogiue et al.
patent: 5115408 (1992-05-01), Darley et al.
patent: 5119314 (1992-06-01), Hotta et al.
patent: 5245224 (1993-09-01), Suzuki et al.
patent: 5300835 (1994-04-01), Assar et al.
patent: 5311083 (1994-05-01), Wanlass
patent: 5352942 (1994-10-01), Tanaka et al.
patent: 5517132 (1996-05-01), Ohara
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5557533 (1996-09-01), Koford et al.
patent: 5559464 (1996-09-01), Orii et al.
patent: 5594368 (1997-01-01), Usami
patent: 5612892 (1997-03-01), Almulla
patent: 5661413 (1997-08-01), Tomita et al.
patent: 5723986 (1998-03-01), Nakashiro et al.
Kojima et al., "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry", 1994 IEEE, Symposium on VLSI Circuits Digest of Technical Papers, pp. 23-24.
Mou et al., "Overturned-Stairs Adder Trees and Multiplier Design", IEEE Transactions on Computers 41 (1992), No. 8, pp. 940-948.
Hill et al., "Digital Systems: Hardware Organization and Design", 1978, p. 257.
Taub et al., "Digital Integrated Electronics", 1977, p. 246.
Goodby et al., "A High-Level Synthesis Methodology for Low-Power VLSI Design", 1994 IEEE Symposium on Low Power Electronics, pp. 48-49.
K. Usami et al., "Clustered Voltage Scaling Technique for Low-Power Design", pp. 3-8, Apr. 1995.
Goodby et al. ("Microarchitectural synthesis of performance-constrained, low-power VLSI designs", IEEE Comput. Soc. Press, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 10, 1994).
Chandrakasan et al. ("Optimizing power using transformations", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 1, Jan. 1995, pp. 12-31).
Goodby et al. ("A High-Level Synthesis Methodology for Low-Power VLSI Design", 1994 IEEE Symposium on Low Power Electronics, Oct. 10, 1994, pp. 48-49).
Usami et al. ("Clustered Voltage Scaling Technique for Low-Power Design", Proceedings of the 1995 International Symposium on Low Power Design, Low Power Design Symposium, Apr. 23, 1995, pp. 3-8).
PTO 99-0683 (Translation of Japanese Published Unexamined (Tokkyo Koho) Patent Application No. 04-223,616; published Aug. 13, 1992; Application No. 02-406,042, filed Dec. 25, 1990; invented by Takayasu Skurai et al.; translated by Translations Branc, Dec. 4, 1998.
PTO 99-0682 (Translation of Japanese Published Unexamined (Kokai) Patent Application No. H2-187063, published Jul. 23, 1990; Application No. H1-7315, filed Jan. 13, 1989; Invented by Akinori Matsuda; translated Nov. 25, 1998 by Translation Branch o.
C. Mead, "Introduction to VLSI systems", pp. 75-76, Addison-Wesley, 1980.
T. Wecker, et al., "CALLAS-a system for automatic digital synthesis" (1989), West Germany, Informatik Forschung Und Entwicklung, vol. 4, No. 1, pp. 37-54.
H. De Man et al., "Cathedral-II: a silicon compiler for digital signal processing" (Dec. 1986), U.S.A., IEEE Design & Test of Computers, vol. 3, No. 6, pp. 13-25.
E.J. McCluskey, "Logic Design Principles" (1986), Prentice-Hall, pp. 439 & 440.

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