Logic synthesis method

Details Logic synthesis method Logic synthesis method

1991-04-09

1994-02-15

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

052872890

ABSTRACT:
A logic circuit the functions of which have been expressed by a Boolean expression is subdivided, and then each of the subdivided logic circuit portions corresponds to each of the Boolean expressions. A plurality of logic circuits whose functions are equal to each other, whose delay times and gate numbers are different from each other, are synthesized every subdivided circuit portions, and a restriction condition formula is formed by employing the synthesized logic circuit under a restriction condition of the delay time designated by a user. While a linear programming is applied under the restriction condition and the number of gates is used as an objective function, such a logic circuit that the objective function takes a stationary value (a minimum value in the present invention) is selected with respect to each of subdivided portions, whereby an overall logic circuit is constructed.

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Kanwar Jit Singh, et al., "Timing Optimization of Combinational Logic", ICCAD 88, 1988, pp. 282-285. (Provided in English).

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