Logic synthesis for logic array modules

Details Logic synthesis for logic array modules Logic synthesis for logic array modules

1995-05-10

1998-05-19

Trammel, James P.

Boots, shoes, and leggings

364488, 364489, 364490, 364491, G06F 1500

Patent

active

057548242

ABSTRACT:
A general approach to the synthesis of logic array modules (LAMs) is used to implement a multilevel combinational acyclic network. The network consists of abstract gates, which perform primitive logic functions and nets to connect them. The inputs to the entire network are called the primary inputs and the outputs of the entire network are the primary outputs. The first step in the synthesis of the LAMs used to implement the network is to partition the network vertically to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module. The second step is to partition horizontally the plurality of logic segments to reduce the size of the segments to a size that can efficiently be implemented as a logic array module. A symbolic representation is generated in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments.

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