Logic synthesis constraints allocation automating the concurrent

Details Logic synthesis constraints allocation automating the concurrent Logic synthesis constraints allocation automating the concurrent

1998-05-12

2000-07-11

Teska, Kevin J.

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

39550007, 39550008, 395555, G06F 300

Patent

active

060866217

ABSTRACT:
A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit.

REFERENCES:
patent: 5572436 (1996-11-01), Dangelo et al.
patent: 5778216 (1998-07-01), Venkatesh
patent: 5870308 (1999-02-01), Dangelo et al.

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