Logic synthesis apparatus

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing

Reexamination Certificate

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Details

C716S101000, C716S106000, C716S108000, C716S113000

Reexamination Certificate

active

07904858

ABSTRACT:
According to the present invention, there is provided an apparatus for executing logic synthesis for a module having a plurality of clock domains, having: an input unit which inputs circuit description data about a circuit function and a constraint in logic synthesis; a path selection unit which selects a path included in the module using a result obtained by analyzing the circuit description data; a recognition unit which recognizes a start point and an end point of the selected path and recognizes clock domains to which the start point and the end point belong; and a technology library setting unit which sets a technology library for the selected path in accordance with the clock domains to which the start point and the end point belong.

REFERENCES:
patent: 5903475 (1999-05-01), Gupte et al.
patent: 6263483 (2001-07-01), Dupenloup
patent: 6289498 (2001-09-01), Dupenloup
patent: 6295636 (2001-09-01), Dupenloup
patent: 6421818 (2002-07-01), Dupenloup et al.
patent: 2006/0123378 (2006-06-01), Cizl et al.
patent: 5-274390 (1993-10-01), None

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