Logic structure and circuit for fast carry

Boots – shoes – and leggings

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G06F 750

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active

052950905

ABSTRACT:
Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

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patent: 4761759 (1988-08-01), Nakagawa
patent: 4870302 (1989-09-01), Freeman
patent: 4897808 (1990-01-01), Nakagawa et al.
patent: 4920509 (1990-04-01), Hmida et al.
Neil Weste and Kamran Eshraghian, "Principles of CMOS VLSI Design, A Systems Perspective", Addison Wesley Publsihing Company, reprinted Oct. 1985, pp. 317-319.
Mano, "Digital Logic and Computer Design", Chapter 9, pp. 376-378, 1979 by Prentice-Hall, Inc.

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