Logic state analyzer

Details Logic state analyzer Logic state analyzer

1977-05-31

1979-02-13

Thomas, James D.

Boots, shoes, and leggings

324121R, 364521, G06F 314, G01R 1320, G06F 302, G06F 1100

Patent

active

041399030

ABSTRACT:
Clock signals, data words and qualifier signals are received via monitor probes during a data acquisition mode, selected data words being stored in a memory in response to the clock and qualifier signals. The stored data words may then be displayed in a tabular or a map format on a cathode ray tube screen. Data words may be acquired randomly, i.e., in a free-running sampling mode, or acquired selectively by using pattern recognition and delay trigger circuits. Using the tabular display format, data words are displayed as ones and zeroes. Using the map display format, each data word thus acquired is displayed on the CRT screen as a dot during a subsequent display mode. The position of each dot on the CRT screen uniquely identifies its address or state value. The most significant bits determine the vertical position on the CRT screen and the least significant bits determine the horizontal position of the dot. The intensity of the dot indicates the relative frequency of occurrence of that logic state. A trace between dots is utilized as a vector to indicate the sequence in which the data words are acquired, the brightened or intensified end of the vector indicating the direction. The vectors are non-linear so that when logic flow occurs in opposite directions between logic states, the vectors will not overlap and obscure useful information. A cursor is provided to select a map area to be displayed in an expanded map mode, wherein a portion of the map may be displayed on a larger scale. Also, a comparator mode is provided to allow comparison of acquired input data with that stored in an auxiliary memory.

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"Generation of Double Size Characters," IBM Technical Disclosure Bulletin, C. J. Holderness, vol. 13, No. 9, Feb. 1971, pp. 2792-2793.

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