Logic simulator and logic simulation method

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364488, 364489, 364490, 364481, 39518301, 39518309, 39518401, 39518501, 371 3, 371 251, 371 35, 324765, G06G 748, G06F 1500

Patent

active

057062234

ABSTRACT:
A logic simulation device includes an indefinite value generating signal line extracting unit, a propagation deciding unit and a message output unit. The logic simulation device is supplied with circuit connection data of a logic circuit and input signal data employed for simulating the logic circuit. The indefinite value generating signal line extracting unit extracts a signal line which enters a floating state in excess of an allowance time or that causes a collision of logic states as an indefinite value generating signal line. The propagation deciding unit decides whether or not a propagation candidate gate having a propagation input end which is connected with an indefinite value generating signal line is in a state propagating the indefinite value to its output. The propagation deciding unit decides that the indefinite value generating signal line is an error signal line causing an error only when the propagation candidate gate is in a state of propagating the value at the propagation input end. The message output unit outputs a warning message for indicating that the error signal line is a signal line to which the indefinite value generated by an operation of the circuit may be propagated to feed a through current.

REFERENCES:
patent: 3702011 (1972-10-01), Armstrong
patent: 3780277 (1973-12-01), Armstrong et al.
patent: 3882386 (1975-05-01), Vinsani
patent: 3892954 (1975-07-01), Neuner
patent: 3927371 (1975-12-01), Pomeranz et al.
patent: 4308616 (1981-12-01), Timoc
patent: 4418410 (1983-11-01), Goetze et al.
patent: 4601032 (1986-07-01), Robinson
patent: 4668880 (1987-05-01), Shoji
patent: 4715035 (1987-12-01), Boehner
patent: 4761607 (1988-08-01), Shiragasawa et al.
patent: 4769817 (1988-09-01), Krohn et al.
patent: 4771428 (1988-09-01), Acuff et al.
patent: 4852093 (1989-07-01), Koeppe
patent: 4855726 (1989-08-01), Nishio
patent: 4862399 (1989-08-01), Freeman
patent: 4908576 (1990-03-01), Jackson
patent: 4937765 (1990-06-01), Shupe et al.
patent: 4937826 (1990-06-01), Gheenala et al.
patent: 4961156 (1990-10-01), Takasaki
patent: 4965800 (1990-10-01), Farnbach
patent: 5051911 (1991-09-01), Kimura et al.
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5272651 (1993-12-01), Bush et al.
patent: 5400270 (1995-03-01), Fukui et al.
patent: 5404360 (1995-04-01), Suzuki et al.
patent: 5422891 (1995-06-01), Bushnell et al.
patent: 5426770 (1995-06-01), Nuber
patent: 5446748 (1995-08-01), Hasebe et al.
patent: 5513339 (1996-04-01), Agrawal et al.
patent: 5541861 (1996-07-01), Komoda et al.
Ruan et al "Fault Modeling for MOS Digital Circuit . . . " pp. 681-683, 1988 IEEE Aug. 1988.
Wu et al "SEESIM--A Fast Synchronous Sequential Circuit Fault Simulator" pp. 446-449, 1992 IEEE Aug. 1992.
Ogihara et al "Test Generation for Sequential Circuits" pp. 424-427, 1988 IEEE May 1988.
Kitamura "Exact Critical Path Tracing Fault Simulation . . . " pp. 474-477, 1989 IEEE Jan. 1989.
Verilog-XL Reference Manual, vol. 2, Mar. 1991, pp. 6-38 to 6-41, "Gate and Switch Level Modeling".

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Logic simulator and logic simulation method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic simulator and logic simulation method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic simulator and logic simulation method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2335220

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.