Logic simulation system for logic simulation of the semiconducto

Details Logic simulation system for logic simulation of the semiconducto Logic simulation system for logic simulation of the semiconducto

1997-03-27

1999-08-24

Stamber, Eric W.

39550006, G06F 9455

Patent

active

059434899

ABSTRACT:
A logic simulation system which comprises a connection data conversion section to convert the format of the connection data, a dump data generation section to generate and output the dump data, a data pattern generation section to generate and output the data pattern reflecting the chip inside variation, a clock pattern generation section to generate and output the clock pattern reflecting the chip inside variation, an expectation pattern generation section to generate and output the expectation pattern, a logic verification pattern generation section to synthesize the data pattern, the clock pattern and the expectation pattern and generates the logic verification pattern and an operation section to execute the logic simulation.

REFERENCES:
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5353243 (1994-10-01), Read et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5621651 (1997-04-01), Swoboda
patent: 5727221 (1998-03-01), Walsh et al.
patent: 5784291 (1998-07-01), Chen et al.
patent: 5841670 (1998-11-01), Swoboda

Affiliated with

Also associated with

Rating

Logic simulation system for logic simulation of the semiconducto does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic simulation system for logic simulation of the semiconducto, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic simulation system for logic simulation of the semiconducto will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-475103