Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2000-03-02
2004-11-09
Teska, Kevin J. (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S002000, C703S013000, C703S014000, C716S030000, C716S030000
Reexamination Certificate
active
06816828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic simulation method and a system for the same, and more particularly, to a logic simulation method in which higher and lower level simulations can be switched on the way of simulation and a system for the same.
2. Description of the Related Art
A large-scale semiconductor integrated circuit is designed by an automatic designing apparatus. In a design procedure flow of the automatic designing apparatus, the highest level description is compiled into a lower level description. The highest level description describes a desired operation flow in a general purpose program language such as the C language or a dedicated abstraction level description language. The lower level description is such as a register transfer (RT) level description and represents the operation flow using hardware resources such as registers and adders.
There is a case where system simulators have a plurality of simulation models in which abstraction levels are different, as shown in FIG.
1
. In this case, an operation level system simulator
101
carries out the simulation using an operation level simulation model with a higher abstraction level. A register transfer level system simulator
102
cannot be started on the way of the simulation of the operation level system simulator
101
. Similarly, the register transfer level system simulator
102
carries out the simulation using a register transfer level simulation model with a lower abstraction level. The simulation of the operation level simulation model
101
cannot be started on the way of the simulation of the register transfer level system simulator
102
. In this way, the operation level system simulator
101
and the register transfer level system simulator
102
are independent from each other, and are treated as the different ones. It is impossible to switch from one of the system simulations to the other on the way of the simulation.
Generally, a higher level simulation model is used when the simulation speed is important, and a lower level simulation mode is used when precision is important. However, there is sometimes the need to analyze the operation from a time of t
1
to a time of t
2
especially in detail in the simulation for the function verification. When the higher level simulator with the high precision is used from a time of
0
to the time of t
2
for the function verification, it takes a great time.
Mixed simulation technique is known in Japanese Laid Open Patent Application (JP-A-Heisei 5-61934) and “Parallel Logic Simulator WIZDOM” (The 57-th National Conference of Information Processing Society of Japan, 1998). In the mixed simulation technique, a plurality of simulation models with different abstraction levels are switched during the simulation. In these references, the switching is carried out between an instruction level simulation model and a hardware simulation mode. The switching is permitted based on the fact that both of the models have a common circuit structure such as a register. Therefore, when the common circuit structure does not exist in models, the above conventional references can not be applied to the models.
Also, the technique that the simulation switching between a gate circuit level and an electronic circuit level is carried out is known in Japanese Laid Open Patent Application (JP-A-Heisei 7-110826). The data transfer in this switching uses the fact that the terminals of a gate circuit and the terminals of the electronic circuit have one-to-one correspondence, and is carried out through analog-digital conversion in the circuit terminal level.
Also, Japanese Laid Open Patent Application (JP-A-Heisei 10-261002) discloses that a circuit operation is represented by a detailed definition model and a rough definition model using a circuit description form and switching is carried out between the models.
In this way, there are known the switching between the higher level mode and the lower level model which have one-to-one correspondence, and the switching between the models with different details in the same level using the common description form.
However, the structure to hold a simulation state does not have one-to-one correspondence between the highest level programming language description such as an operation level description and the lower level description such as the register transfer level description. As the result, it is not possible to carry out the data transfer between the different level descriptions. Therefore, the switching between models in the simulation is impossible conventionally.
In this way, the establishment of the switching technique between the simulation models of different levels with no one-to-one correspondence in the description is requested for the simulation in the high speed and high precision.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a logic simulation method in which simulation can be switched between higher and lower level models, and a simulation system for the same.
Another object of the present invention is to provide a logic simulation method in which simulation can be switched between higher, middle and lower level models, and a simulation system for the same.
Still another object of the present invention is to provide a recording medium storing a program for one of the above logic simulation methods.
In order to achieve an aspect of the present invention, a logic simulation method is achieved by executing one of an algorithm level simulation corresponding to an algorithm level description and a register transfer level simulation corresponding to a register transfer level description, and by switching one of the algorithm level simulation and the register transfer level simulation into the other in response to a switching instruction using a relation between states of the algorithm level description and states of the register transfer level description. The algorithm level description is associated with arithmetic and logic operations and not associated with logic circuits. The register transfer level description is associated with logic circuits.
Here, the logic simulation method may further include converting the algorithm level description into the register transfer level description.
Also, in the conversion, the algorithm level description is converted into the register transfer level description using a table of usable resources.
Also, the logic simulation method may further includes producing an algorithm level model and a register transfer level model from the algorithm level description and the register transfer level description. The algorithm level simulation and the register transfer level simulation are executed using the algorithm level model and the register transfer level model, respectively.
Also, in the execution, while the one simulation is executed, stopping the other simulation. In this case, in the switching, a variable value set in the one simulation is transferred into the other simulation. Also, in the switching, the other simulation is started in response to the transfer of the variable value set.
Also, the logic simulation method may further include relating states of the algorithm level description and states of the register transfer level description to produce the relation. In this case, for the relation, there is produced an algorithm level model, a state transition diagram indicative of states of the algorithm level simulation, a variable table and a register/variable table indicative of variables set to registers for every state from the algorithm level description. The algorithm level simulation uses the algorithm level model. Also, a register transfer level model, a register table and a variable table is produced from the register transfer level description, the register transfer level simulation using the register transfer level model. Also, a control mechanism is produced through the producing steps. The control mechanism relates states of the algorithm level description and states of the register t
Ferris Fred
NEC Electronics Corporation
Teska Kevin J.
LandOfFree
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