Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2000-07-17
2004-11-02
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S015000, C714S733000
Reexamination Certificate
active
06813598
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to logic simulation methods and logic simulation apparatuses and, more particularly, to a logic simulation method and logic simulation apparatus for testing logic design of the entirety of a semiconductor integrated circuit chip such as a large capacity memory in which a memory cell array is divided into subarrays, an ASIC carrying a large capacity memory, and a system LSI.
2. Description of the Related Art
In testing logic design of the entirety of a semiconductor integrated circuit chip such as a large capacity memory in which a memory cell array is divided into subarrays, an ASIC carrying a large capacity memory, and a system LSI, a logic simulation method and a logic simulation apparatus implementing the method are used. The logic simulation method and the logic simulation apparatus enable top-down design or bottom-up design by describing an arrangement of memory cell arrays and sense amplifiers using an operation mode so that the size of memory consumed in (process size) and the time required for execution of logic simulation are reduced. The above-described related-art logic simulation method and the logic simulation apparatus implementing the method use models effective at the level of transistors and gate elements. As compared with other simulation procedures executing logic simulation of all the circuit models, the method and apparatus described above are capable of reducing the size of memory consumed in logic simulation and the time required for execution of logic simulation.
In the above-described related-art logic simulation method and apparatus, memory cell arrays, subdecoders, sense amplifiers and I/O gates that constitute a memory core part are treated as separate blocks. Operation models of the memory cell arrays and the sense amplifiers are created. With regard to the subdecoders and the I/O gates, operation models effective at the level of transistor and elements are created to perform simulation.
Since the logic simulation method and apparatus according to the related art are constructed as described above, the number of events such as exchange of signals between blocks and variation in signal level grow to an extent that a sufficient simulation performance is not obtained.
SUMMARY OF THE INVENTION
Accordingly, a general object of the present invention is to provide a logic simulation method and a logic simulation apparatus in which the aforementioned problem is eliminated.
Another and more specific object of the present invention is to provide a logic simulation apparatus and a logic simulation method for use in testing logic design of the entirety of a semiconductor integrated circuit chip such as a large capacity memory, an ASIC carrying a large capacity memory, and a system LSI, in which the size of memory consumed in simulation and the time required for simulation are reduced so that a sufficient simulation performance is provided.
The aforementioned objects can be achieved by a mixed-level logic simulation apparatus comprising: memory cell array subdecoder operation model providing means for providing an operation model corresponding to a memory cell array and a subdecoder circuit; a sense amplifier and I/O gate operation model providing means for providing an operation model corresponding to a sense amplifier and an I/O gate circuit; a transistor and gate element operation model providing means for providing an operation model of a transistor and a gate element; circuit connection data providing means for providing circuit connection data prescribing connection of logic circuits; input test pattern providing means for providing a test pattern to an input part of the logic circuit; function and logic simulation means for executing logic simulation of the logic circuit based on the input test pattern; simulation result displaying means for displaying a result of simulation obtained by the function and logic simulation execution means in order to verify that a function of the logic circuit is realized, wherein circuit operation of the logic circuit comprising transistors, logic gates and functional blocks is tested using models of switches, gates and functions.
The memory cell array subdecoder operation model providing means may build an operation model by regarding the memory cell array and the subdecoder as one block; and the memory cell array subdecoder operation providing means may comprise: first signal variation detection means for detecting a variation in signal level occurring on a main word signal line, a subdecode signal line and a bit signal line; MWL signal encoding means for encoding a signal on the main word signal line; MWL signal encoded value retaining means for retaining an MWL signal encoded value obtained by the MWL signal encoding means; SD signal encoding means for encoding a signal on the subdecode signal line; SD signal encoded value retaining means for retaining an SD signal encoded value obtained by the SD signal encoding means; WL calculation means for calculating a WL value for a word number indicating a selected word line, based on the MWL signal encoded value and the SD signal encoded value; WL value retaining means for retaining the WL value obtained by the WL calculating means; memory cell data retaining means for retaining logic data corresponding to a memory cell having a size corresponding to a number obtained by multiplying a bitwise width of the word line indicated by the WL value stored in the WL value retaining part and a bitwise width of a bit signal line; first input and output operation means for allowing one-word data in the memory cell selected by the WL value to be read and written via the bit signal line; and first read and write control means for controlling a read status and a write status of the first input and output operation means, based on a signal level occurring on the bit signal line.
The sense amplifier and I/O gate operation model providing means may build an operation model by regarding the sense amplifier and the I/O gate as one block; and the sense amplifier and I/O gate operation model providing means may comprise: second signal variation detecting means for detecting variation in signal level on the bit signal line, a column selection line, a global IO line, a bit line connection control signal line, a bit line equalizing signal line and a sense enable signal line; CSL signal encoding means for encoding a signal on the column selection line; CSL signal encoded value retaining means for retaining a CSL signal encoded value obtained by the CSL signal encoding means; sense amplifier data retaining means for retaining logic data corresponding to the sense amplifier register corresponding to the bitwise width of the bit signal line; second input and output operation means for allowing data in the sense amplifier register data retaining means, which data is selected based on the CSL signal encoded value stored in the CSL signal encoded value retaining part, to be read and written via the global IO signal line; third input and output operation means for allowing data in the sense amplifier register data retaining means to be read and written via the bit signal line; and second read and write control means for controlling a read status and a write status of the second input and output operation means and the third input and output operation means, based on a signal level occurring on the bit signal line, the global IO signal line, the bit line connection control signal line, the bit line equalizing signal line and the sense enable signal line.
The first signal variation detection means may determine whether at least one of the bits occurring on plural-bit signal lines having a width of a plurality of bits subject to encoding is 1, the plural-bit signal lines including the main word signal line and the subdecode signal line; and wherein when it is determined that at least one of the bits is 1, a determination is made as to which bit of the plurality of bits constituting a plural-bit signal is selected.
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Broda Samuel
Burns Doane Swecker & Mathis L.L.P.
Thangavelu Kandasamy
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